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US 2009/0289677 A1Published application
Device
AssigneeElpida Memory, Inc.
InventorsYoshio Mizukane, Hiroki Fujisawa
Life of this patent
Estimating the term…
Abstract
A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.
Claims20
A device comprising:
- a DLL circuit that generates an internal clock signal based on an input signal inputted externally;
- a clock generation circuit that generates a first clock signal based on the input signal;
- and
- a counter circuit that counts the first clock signal supplied from the clock generation circuit in order to obtain a start-up period required for the DLL circuit to transit from a non-operating state to an operating state, supplies the DLL circuit with a DLL output control signal to inactivate the internal clock signal during the start-up period, and supplies the clock generation circuit with a clock generation control signal to activate or inactivate the first clock signal.
1 more element
A device comprising:
- an internal circuit;
- a DLL circuit to generate a first clock signal;
- a counter circuit to control to supply the first clock signal to the internal circuit and to be inactivated after allowing to supply the first clock signal to the internal circuit.
Dependencies are inferred from the claim text.