Voltage controlled oscillators and phase-frequency locked loop circuit using the same
AssigneeMediatek Inc.
InventorPao-Cheng CHIU
Life of this patent
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Abstract
A voltage controlled oscillator comprising first and second differential delay cells. The first differential delay cell has a first control voltage input terminal. The second differential delay cell is coupled to the first differential delay cell in a loop and has a second control voltage input terminal. The second voltage input terminal is disconnected from the first voltage control input terminal. The first voltage control input terminal receives a first voltage signal, and the second voltage control input terminal receives a second voltage signal different from the first voltage signal.
Claims17
A voltage controlled oscillator comprising:
- a first differential delay cell having a first control voltage input terminal;
- and
- a second differential delay cell coupled to the first differential delay cell in a loop and having a second control voltage input terminal which is disconnected from the first voltage control input terminal;
- wherein the first voltage control input terminal receives a first voltage signal, and the second voltage control input terminal receives a second voltage signal different from the first voltage signal.
A voltage controlled oscillator comprising:
- a first differential delay cell having a first control voltage input terminal;
- and
- a second differential delay cell coupled to the first differential delay cell in a loop and having a second control voltage input terminal which is disconnected from the first voltage control input terminal;
- wherein the first voltage control input terminal receives a first voltage signal with an adjustable level, and the second voltage control input terminal receives a second voltage signal with a fixed level.
A voltage controlled oscillator comprising:
- a first differential delay cell having a control voltage input terminal;
- and
- a second differential delay cell coupled to the first differential delay cell in a loop;
- wherein the control voltage input terminal receives a voltage signal with an adjustable level, the delay time of the second differential delay cell is fixed.
A phase-frequency locked loop circuit comprising:
- a voltage controlled oscillator controlled by a first voltage signal and a second voltage signal and generating an output clock at an output terminal according to the first and second voltage signals;
- a frequency locked circuit receiving a reference clock and the output clock and adjusting the first voltage signal according to the reference clock and the output clock;
- a phase locked circuit receiving a data input signal and the output clock and adjusting the second voltage signal according to the data input signal and the output clock.
A phase-frequency locked loop circuit comprising:
- a phase-frequency detector receiving a reference clock and a feedback clock and generating an indication signal according to the difference between the reference clock and the feedback clock;
- a charge pump receiving the indication signal, generating a first voltage signal, and adjusting a level of the first voltage signal according to the indication signal;
- a voltage controlled oscillator controlled by the first voltage signal and generating an output clock at an output terminal, wherein the voltage controlled oscillator comprises:
- a first differential delay cell having a first control voltage input terminal for receiving the first voltage signal, wherein the delay time of the first differential delay cell is determined by the adjusted level of the first voltage signal;
- and
- a second differential delay cell coupled to the first differential delay cell in a loop, wherein the delay time of the second differential delay cell is fixed;
- and
- a frequency divider dividing the frequency of the output clock to serve as the feedback for the phase-frequency detector.
Dependencies are inferred from the claim text.