# US 2009/0289670 A1 · Semiconductor integrated circuit device

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- Number: US 2009/0289670 A1
- Document ID: US20090289670A1
- Status: Published application
- Kind: A1
- Application number: 12/471,720
- Filed: 2009-05-26
- Published: 2009-11-26
- Earliest claimed: 2008-05-26
- Assignees: Fuji Electric Device Technology Co., Ltd.
- Inventors: Yoshiaki TOYODA; Kenichi ISHII; Morio IWAMIZU
- Web page: https://patentgrep.com/patent/US20090289670A1

## CPC

- H03K 17/0828: {in composite switches}
- H03K 17/06: Modifications for ensuring a fully conducting state
- H03K 2017/066: {Maximizing the OFF-resistance instead of minimizing the ON-resistance}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A buffer circuit is provided between a gate terminal of a pull-down transistor and a threshold circuit receiving a gate signal as an input signal. A voltage applied to an output terminal of a power semiconductor element from an external battery power supply is supplied to the buffer circuit through a resistive element. The buffer circuit converts the level of an on-signal output from the threshold circuit into a voltage higher than the threshold of the pull-down transistor, so that the pull-down transistor operates surely to turn off the power semiconductor element even when the level of the gate signal is low. Thus, there is provided a semiconductor integrated circuit device having a power semiconductor element which can be turned off by sure operation of a pull-down semiconductor element.

## Claims

### Claim 1

A semiconductor integrated circuit device comprising:
a power semiconductor element including an output terminal supplied with a power supply voltage externally and which applies an output current to the output terminal based on a gate signal input externally;
a pull-down semiconductor element which pulls down a gate voltage of the power semiconductor element to an off level of the power semiconductor element based on the gate signal;
a threshold circuit which outputs an on-signal or an off-signal for turning on or off the pull-down semiconductor element based on the gate signal;
a buffer circuit which converts the level of the on-signal output from the threshold circuit into a level for turning on the pull-down semiconductor element; and
a resistive element which is connected to the output terminal of the power semiconductor element;
wherein the buffer circuit is driven by a voltage extracted from the output terminal through the resistive element.

### Claim 2 (depends on 1)

A semiconductor integrated circuit device according to claim 1, wherein the power semiconductor element is a lateral power MOS transistor or a lateral IGBT.

### Claim 3 (depends on 2)

A semiconductor integrated circuit device according to claim 2, wherein the resistive element is a diffused resistor formed in a surface region of a semiconductor substrate or a polysilicon resistor formed through an insulating film on the semiconductor substrate.

### Claim 4 (depends on 1)

A semiconductor integrated circuit device according to claim 1, wherein the power semiconductor element is a vertical IGBT or a vertical power MOS transistor.

### Claim 5 (depends on 4)

A semiconductor integrated circuit device according to claim 4, wherein the resistive element is a depression MOS semiconductor element.