Systems and methods for providing defect-tolerant logic devices
OwnerMaryam Ashouei, Adit D. Singh +1inventors
InventorsMaryam Ashouei, Adit D. Singh, Abhijit Chatterjee
Life of this patent
Estimating the term…
Abstract
The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.
Claims20
A defect-tolerant logic device comprising:
- a plurality of CMOS gates;
- at least one defective CMOS gate included within the plurality of CMOS gates;
- wherein the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective;
- and
- wherein the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.
A method for correcting a defective logic device, the method comprising:
- receiving a diagnosis of at least one defective CMOS gate among a plurality of CMOS gates of a logic device;
- reconfiguring the at least one defective CMOS gate to a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective;
- and
- reconfiguring the at least one defective CMOS gate to a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.
A method increasing yield in logic device manufacturing, the method comprising:
- fabricating a plurality of logic devices;
- diagnosing at least one defective logic device from the plurality of logic devices;
- diagnosing at least one defective CMOS gate in the at least one defective logic device;
- reconfiguring the at least one defective CMOS gate to an pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective;
- and
- reconfiguring the at least one defective CMOS gate to a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.
Dependencies are inferred from the claim text.