Inspection apparatus and method for semiconductor IC
AssigneePanasonic Corporation
InventorsNaomi Miyake, Yoshiro Nakata
Life of this patent
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Abstract
The connection between a PTC element 22a corresponding to each semiconductor IC 11a and a power-supply line 25a is performed via a relay, a high voltage is supplied to the power-supply line 25a by sequentially turning on the relays, and a high voltage is supplied to each PTC element 22a in order, whereby it is possible to trip beforehand a PTC element 22a connected to a DC-defective semiconductor IC 11a. In this state, wafer level burn-in is performed together, which enables the PTC element 22a to be positively tripped during the burn-in for the DC defect of the semiconductor IC 11a, with the result that it is possible to increase the reliability of the burn-in.
Claims10
-3. (canceled)
A semiconductor IC inspection method for performing burn-in for a plurality of semiconductor ICs, with power supply stopped to a semiconductor IC, by a PTC element, the method comprising the steps of:
- supplying power to the semiconductor ICs singly or in a plurality of numbers at a time in order and tripping the PTC element connected to any defective semiconductor IC, and
- performing burn-in for each semiconductor, IC with a tripped PTC element.
- wherein for each semiconductor IC having multiple power supplies, an output of a PTC element corresponding to a first power supply is capable of controlling a voltage to a PTC element corresponding to a second power supply by a relay connected to the PTC element corresponding to a first power supply.
(canceled)
-13. (canceled)
Dependencies are inferred from the claim text.