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US 2009/0289614 A1Published application
Reference buffer circuit
AssigneeMediatek Inc.
InventorsWei-Hsuan TU, Tzung-Hung KANG
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Abstract
A reference buffer circuit with high driving capability is disclosed. In which, a buffering stage has a first NMOS transistor and a first PMOS transistor to provide high and low tracking voltages respectively based on a high input voltage and a low input voltage. A first driving stage is driven by the high and low tracking voltages to output a first high output voltage and a first low output voltage. A body of the first PMOS transistor is tied to a first bias voltage lower than a supply voltage for the buffering and first driving stages.
Claims20
A reference buffer circuit, comprising:
- a buffering stage, for providing a high tracking voltage and a low tracking voltage respectively based on a high input voltage and a low input voltage;
- and
- a first driving stage, driven by the high tracking voltage and the low tracking voltage to output a first high output voltage and a first low output voltage,
- wherein the buffering stage comprises:
- a first NMOS transistor with its drain coupled to a first supply voltage;
- a first operational amplifier, having a first input end for receiving the high input voltage, a second input end coupled to a source of the first NMOS transistor, and an output end coupled to a gate of the first NMOS transistor for outputting the high tracking voltage;
- a first PMOS transistor with its drain coupled to a signal ground;
- and
- a second operational amplifier, having a first input end for receiving the low input voltage, a second input end coupled to a source of the first PMOS transistor, and an output end coupled to a gate of the first PMOS transistor for outputting the low tracking voltage;
- wherein a body of the first PMOS transistor is tied to a first bias voltage lower than the first supply voltage.
7 more elements
A reference buffer circuit, comprising:
- a buffering stage, having a first NMOS transistor and a first PMOS transistor for providing a high tracking voltage and a low tracking voltage respectively based on a high input voltage and a low input voltage;
- and
- a first driving stage, having a second NMOS transistor and a second PMOS transistor respectively driven by the high tracking voltage and the low tracking voltage to output a first high output voltage and a first low output voltage, wherein a body of the first PMOS transistor is tied to a first bias voltage lower than a first supply voltage for the buffering and first driving stages.
Dependencies are inferred from the claim text.