Low Inductance Ball Grid Array Device Having Chip Bumps on Substrate Vias

A method for fabricating an electronic device comprising the steps of:

• providing an insulating substrate having a first and a second surface, a periphery, and a central region surrounded by peripheral regions;
• opening through-holes in the substrate, the through-holes extending from the first to the second surface, whereby a first plurality of through-holes spreads throughout the central region and a second plurality of through-holes spreads throughout the peripheral regions;
• depositing a metal foil on the first surface, the foil covering the through-holes;
• patterning the metal foil by forming lands and traces, the lands located over the through-holes of the first and the second plurality, and the traces connecting each land to the periphery;
• disposing an insulator mask on the first surface and the patterned foil;
• providing a semiconductor chip having metal bumps on a first and a second set of terminals, the first set in the locations of the first plurality of through-holes;
• opening windows in the mask, the windows located in the central substrate region and positioned to expose the lands of the first through-hole plurality, and further to expose certain trace portions, which match the second set of chip terminal locations;
• depositing coats of bondable and solderable metals on the exposed lands and trace portions, as well as in the through-holes, thereby preparing the exposed lands and trace portions to become bump pads and transforming the through-holes to become conductive vias;
• assembling the chip on the substrate by attaching the chip bumps to the bump pads, whereby the first set chip terminals are positioned over the lands on the vias in the first plurality of through-holes;
• and
• attaching solder bodies to the vias on the second substrate surface, thereby completely filling the vias to create a metallic short-path from the solder bodies to the chip terminals.