# US 2009/0289322 A1 · Memory devices having a carbon nanotube

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- Number: US 2009/0289322 A1
- Document ID: US20090289322A1
- Status: Published application
- Kind: A1
- Application number: 12/469,295
- Filed: 2009-05-20
- Published: 2009-11-26
- Earliest claimed: 2008-05-20
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Seong-Ho Moon; Hong-Sik Yoon; Subramanya Mayya; Sun-Woo Lee; Dong-Woo Kim; Xiaofeng Wang
- Web page: https://patentgrep.com/patent/US20090289322A1

## CPC

- G11C 13/025: {using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 23/00: Digital stores characterised by movement of mechanical parts to effect storage, e.g. using balls; Storage elements therefor
- H10B 99/16: {comprising memory cells having diodes}
- G11C 2213/16: Memory cell being a nanotube, e.g. suspended nanotube
- H10K 10/23: Schottky diodes
- H10K 10/491: {Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]}
- H10K 85/221: {Carbon nanotubes}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10B: ELECTRONIC MEMORY DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

In a memory device having a carbon nanotube and a method of manufacturing the same, the memory device includes a lower electrode, an upper electrode having a first void exposing a sidewall of a diode therein, an insulating interlayer pattern having a second void exposing a portion of the lower electrode between the lower electrode and the upper electrode, and a carbon nanotube wiring capable of being electrically connected with the diode of the upper electrode by a voltage applied to the lower electrode. The memory device may reduce generation of a leakage current in a cross-bar memory.

## Claims

### Claim 1

A memory device having a carbon nanotube, comprising:
a lower electrode;
an upper electrode including a diode in a first void of the upper electrode wherein a sidewall of the first void exposes the diode;
an insulating interlayer pattern between the lower electrode and the upper electrode, wherein the insulating interlayer pattern includes a second void connected with the first void, wherein the second void exposes a portion of the lower electrode; and
carbon nanotube wiring electrically connected to the exposed portion of the lower electrode and extending through the second void into the first void so that a free moving portion of the carbon nanotube wiring is positioned adjacent to the sidewall of the first void, wherein the free moving portion of the carbon nanotube wiring is configured to move to electrically contact the diode at the sidewall of the first void of the upper electrode responsive to a voltage applied to the lower electrode.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the lower electrode is at least one lower wiring extending in a first direction, and the upper electrode is at least one upper wiring extending in a second direction perpendicular to the first direction.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the first void has a width larger than a width of the second void.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the upper electrode comprises a diode including a first polysilicon pattern doped with n-type impurities and a second polysilicon pattern doped with p-type impurities.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the second polysilicon pattern doped with p-type impurities has a sidewall exposed by the first void, and the first polysilicon pattern doped with n-type impurities horizontally surrounds the second polysilicon pattern.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the upper electrode comprises a diode including a first polysilicon pattern doped with n-type impurities and a second polysilicon pattern doped with p-type impurities, and at least one metal pattern horizontally surrounding the diode.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the diode is a P-N junction diode or a Schottky diode.

### Claim 8 (depends on 1)

The memory device of claim 1, further comprising a catalyst layer formed on the lower electrode.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the lower electrode and the upper electrode have a bar shape, and two bars of the lower electrode and the upper electrode cross each other.

### Claim at position 10

10-16. (canceled)

### Claim 17

A memory device including a carbon nanotube, comprising:
an upper electrode of a memory cell including a diode in an upper portion of a stepped profile void therein having upper and lower sidewalls offset from one another wherein the upper sidewall exposes the diode.