US 2009/0289291 A1 · SOI DEEP TRENCH CAPACITOR EMPLOYING A NON-CONFORMAL INNER SPACER

Abstract

A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.

Claims10

Dependent claims

1-14. (canceled)

A semiconductor structure comprising:

a semiconductor-on-insulator (SOI) substrate including a vertical stack, from bottom to top, of a bottom semiconductor layer, a buried insulator layer, and a top semiconductor layer, wherein a bottommost surface of said top semiconductor layer contacts a topmost surface of said buried insulator layer;
an access transistor including a source region that is located in said top semiconductor layer;
a bottle shaped trench located in said semiconductor-on-insulator (SOI) substrate, wherein a lower portion of said bottle shaped trench underneath said buried insulator layer is wider than an upper portion of said bottle shaped trench;
an inner electrode comprising a conductive material having a top surface located between said topmost surface of said buried insulator layer and a bottom surface of said buried insulator layer;
a conductive buried strap laterally contacting said source region and vertically contacting said inner electrode;
and
a graded thickness dielectric collar having a thickness that monotonically decreases with distance from a top surface of said top semiconductor layer.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

12/124,186Filed 21 May 2008

Published

26 Nov 2009

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 1/665
Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors: trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors
H10B 12/0387
The capacitor being in a trench in the substrate: making the trench
H10D 1/047
Of capacitors having potential barriers, e.g. varactors: of conductor-insulator-semiconductor capacitors, e.g. trench capacitors
H10D 86/01
Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless…

Soi deep trench capacitor employing a non-conformal inner spacer

Life of this patent

Soi deep trench capacitor employing a non-conformal inner spacer

Life of this patent

Abstract

Claims10