Integrated circuit including an insulating structure below a source/drain region and method
AssigneeQimonda AG
InventorDongping Wu
Life of this patent
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Abstract
An integrated circuit including an insulating structure below a source/drain region and a method. One embodiment includes a memory cell with an access transistor and a storage element. A first source/drain region of the access transistor is electrically coupled to the storage element. A first insulating structure is disposed between the first source/drain region and a first portion of a semiconductor substrate, the first portion being arranged below the first source/drain region. A channel region of the access transistor is formed between the first and a second source/drain region of the access transistor in an active area being electrically coupled to the first portion of the semiconductor substrate.
Claims22
An integrated circuit comprising:
- a memory cell including an access transistor and a storage element, comprising:
- a first source/drain region is electrically coupled to the storage element;
- a first insulating structure disposed between the first source/drain region and a first portion of a semiconductor substrate;
- and
- a channel region formed between the first and a second source/drain region in an active area being electrically coupled to the first portion of the semiconductor substrate.
An integrated circuit comprising:
- a transistor comprising:
- a first source/drain region,
- a channel region formed between the first and a second source/drain region in an active area of a semiconductor substrate, and
- a gate electrode, configured to control a conductivity of the channel region, wherein the gate electrode is arranged adjacent to three sides of the channel region;
- and
- a first insulating structure being part of the integrated circuit and being disposed between the first source/drain region and a first portion of the semiconductor substrate, the first portion being arranged below the first source/drain region;
- wherein the active area is electrically coupled to the first portion of the semiconductor substrate.
A method of manufacturing an integrated circuit, the method comprising:
- forming a first insulating structure above a first portion of a semiconductor substrate;
- forming an access transistor, wherein a first source/drain region is formed above the first insulating structure and wherein a channel region is formed such that it is electrically coupled to the first portion of the semiconductor substrate;
- and
- forming a connecting structure configured to electrically couple the first source/drain region of the access transistor to a storage element.
A method of manufacturing an integrated circuit, the method comprising:
- forming a first groove in a semiconductor substrate above a first portion of the semiconductor substrate;
- forming a first insulating structure at a bottom portion of the first groove;
- forming a first source/drain region of an access transistor above the first insulating structure;
- forming a channel region of the access transistor such that it is electrically coupled to the first portion of the semiconductor substrate;
- and
- forming a connecting structure, configured to electrically couple the first source/drain region of the access transistor to a storage element.
An integrated circuit comprising:
- a memory cell including an access transistor and a storage element, the access transistor comprising:
- a first source/drain region of the access transistor is electrically coupled to the storage element;
- means for reducing leakage current disposed between the first source/drain region and a first portion of a semiconductor substrate;
- and
- a channel region formed between the first and a second source/drain region of the access transistor in an active area being electrically coupled to the first portion of the semiconductor substrate.
Dependencies are inferred from the claim text.