Method for Making Transistors and the Device Thereof

A CMOS fabrication process for forming a semiconductor integrated circuit, comprising:

• forming a first semiconductor layer having a <100> channel orientation, where the first semiconductor layer comprises a PMOS device portion and an NMOS device portion;
• epitaxially growing a biaxially compressive semiconductor layer on the PMOS device portion and not on the NMOS portion of the first semiconductor layer;
• forming PMOS and NMOS gate structures, comprising:
• at least a PMOS gate structure overlying the biaxially compressive semiconductor layer to define a PMOS transistor channel region, the PMOS transistor channel region comprising at least a portion of the biaxially compressive semiconductor layer below the PMOS gate structure, and
• at least an NMOS gate structure overlying the NMOS device portion of the first semiconductor layer to define a NMOS transistor channel region in the NMOS device portion of the first semiconductor layer below the NMOS gate structure;
• and
• forming one or more contact etch stop layers over the NMOS and PMOS gate structures.

A semiconductor device comprising:

• a silicon substrate having a <100> channel orientation;
• a biaxially compressive silicon germanium layer that is epitaxially grown on the substrate;
• a PMOS gate structure overlying the biaxially compressive silicon germanium layer to define a PMOS transistor channel region in a portion of the biaxially compressive silicon germanium layer below the PMOS gate structure;
• and
• a neutral or compressive contact etch stop layer formed over the PMOS gate structure;
• and
• source and drain regions formed in the substrate adjacent to the PMOS transistor channel region.