# US 2009/0269902 A1 · Capacitor having tapered cylindrical storage node and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2009/0269902 A1 - Document ID: US20090269902A1 - Status: Published application - Kind: A1 - Application number: 12/499,248 - Filed: 2009-07-08 - Published: 2009-10-29 - Earliest claimed: 2006-12-29 - Assignees: Hynix Semiconductor Inc. - Inventors: Ho Jin CHO; Cheol Hwan PARK; Jae Soo KIM; Dong Kyun LEE - Web page: https://patentgrep.com/patent/US20090269902A1 ## CPC - H10D 1/694: {comprising noble metals or noble metal oxides} - H10B 12/033: {the capacitor extending over the transistor} - H10D 1/042: {using deposition processes to form electrode extensions} - H10D 1/716: {having vertical extensions} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node. ## Claims ### Claim 1 A method for manufacturing a capacitor, comprising the steps of: forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate provided with a storage node contact plug; etching the mold insulation layer and the etching stop layer to form a first hole in an upper portion of the storage node contact plug; depositing a tapering layer over the mold insulation layer including inside the first hole, wherein the thickness of the tapering layer at an upper end portion is thicker that than the thickness of the tapering layer at a lower end portion; etching back the tapering layer and the buffer oxide layer so that a second hole for exposing the storage node contact plug is formed, wherein the tapering layer is remained only at an upper end portion of the second hole; forming a metal layer for a storage node on the surface of the second hole including the remaining tapering layer at an upper end portion of the second hole; removing the mold insulation layer and the remaining tapering layer to form a cylindrical storage node, wherein an upper end portion of the cylindrical storage node has a tapered shape; and forming a dielectric layer and a plate node over the storage node. ### Claim 2 (depends on 1) The method for manufacturing a capacitor according to claim 1, wherein the etching stop layer is a nitride layer. ### Claim 3 (depends on 1) The method for manufacturing a capacitor according to claim 1, wherein the mold insulation layer is a single layer of PE-TEOS or a double layer of PSG layer and PE-TEOS layer. ### Claim 4 (depends on 1) The method for manufacturing a capacitor according to claim 1, wherein the tapering layer is formed as an oxide layer of one of a PE-TEOS layer, a PE-USG layer, an O3-USG layer, a LP-TEOS layer, a HTO layer, and a SiON layer. ### Claim 5 (depends on 1) The method for manufacturing a capacitor according to claim 1, wherein the tapering layer is formed in a CVD or PECVD process. ### Claim 6 (depends on 1) The method for manufacturing a capacitor according to claim 1, wherein the tapering layer is deposited to a thickness of 50 to 500 Å at an upper end portion of the first hole and to a thickness of 10 to 100 Å at a lower end portion of the first hole. ### Claim 7 (depends on 1) The method for manufacturing a capacitor according to claim 1, wherein the tapering layer remaining at an upper end portion of the second hole has a thickness of 20 to 100 Å. ### Claim 8 (depends on 1) The method for manufacturing a capacitor according to claim 1, further comprising the step of forming a metal silicide layer over the storage node contact plug, after etching back the tapering layer and the buffer oxide layer but before forming the metal layer for the storage node. ### Claim 9 (depends on 8) The method for manufacturing a capacitor according to claim 8, wherein the metal silicide layer is a TiSix layer. ### Claim 10 (depends on 1) The method for manufacturing a capacitor according to claim 1, wherein the storage node is a metal layer made of at least one of TiN, WN, TaN, Ru, and Pt. ### Claim 11 (depends on 1) The method for manufacturing a capacitor according to claim 1, wherein the dielectric layer is formed as one of a ZrO2 layer, an Al2O3 layer, and a laminated layer of Al2O3 layer and ZrO2 layer. ### Claim 12 (depends on 11) The method for manufacturing a capacitor according to claim 11, wherein the Al2O3 layer and ZrO2 layer are formed using Zr[N(CH3)] 2, Zr[N(CH2CH3)] 2, or Zr[N(CH3) (CH2CH3)] 2 as a source of Zr, using Al(Ch3) 3 as a source of Al, and using O3 or H2O as a source of O according to an ALD process at a temperature of 200 to 480° C. ### Claim 13 (depends on 1) The method for manufacturing a capacitor according to claim 1, wherein the plate node is a metal layer made of at least one of TiN, WN, TaN, Ru, and Pt. ### Claim 14 (depends on 13) The method for manufacturing a capacitor according to claim 13, wherein the TiN layer is formed as a double layer according to the CVD and PVD processes or a double layer according to the ALD and PVD processes. ### Claim 15 A method for manufacturing a capacitor, comprising the steps of: forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate provided with a storage node contact plug; etching the mold insulation layer, the etching stop layer, and the buffer oxide layer to form a hole for exposing the storage node contact plug; depositing a tapering layer over the mold insulation layer including inside the hole, wherein the thickness of the tapering layer at an upper end portion is thicker that than the thickness of the tapering layer at a lower end portion; etching back the tapering layer to expose the storage node contact plug, wherein the tapering layer is remained only at an upper end portion of the hole; forming a metal layer for a storage node on the surface of the hole including the remaining tapering layer at an upper end portion of the hole; removing the mold insulation layer and the remaining tapering layer to form a cylindrical storage node, wherein an upper end portion of the cylindrical storage node has a tapered shape; and forming a dielectric layer and a plate node over the storage node. ### Claim 16 (depends on 15) The method for manufacturing a capacitor according to claim 15, wherein the tapering layer is formed in a CVD or PECVD process. ### Claim 17 (depends on 15) The method for manufacturing a capacitor according to claim 15, wherein the tapering layer is deposited to a thickness of 50 to 500 Å at an upper end portion of the hole and to a thickness of 10 to 100 Å at a lower end portion of the hole. ### Claim 18 (depends on 15) The method for manufacturing a capacitor according to claim 15, wherein the tapering layer remaining at an upper end portion of the hole has a thickness of 20 to 100 Å.