# US 2009/0267162 A1 · Method of manufacturing semiconductor device and semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2009/0267162 A1 - Document ID: US20090267162A1 - Status: Published application - Kind: A1 - Application number: 12/403,780 - Filed: 2009-03-13 - Published: 2009-10-29 - Earliest claimed: 2008-04-25 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Kazuaki Nakajima - Web page: https://patentgrep.com/patent/US20090267162A1 ## CPC - H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)} - H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET} - H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)} - H10D 64/01338: {with a treatment, e.g. annealing, after the formation of the conductor} - H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)} - H10D 64/685: {being perpendicular to the channel plane} - H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)} - H10D 84/0167: {Manufacturing their channels} - H10D 84/0177: {the gate conductors having different materials or different implants} - H10D 84/0181: {Manufacturing their gate insulating layers} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A method of manufacturing a semiconductor device comprises: forming a gate insulator on a substrate, the gate insulator including a high-dielectric film in whole or part; forming a first metal film on the gate insulator; forming a second metal film on the first metal film; and forming a reaction film between the gate insulator and the first metal film by letting the high-dielectric film and the first metal film react with each other through a thermal treatment. ## Claims ### Claim 1 A method of manufacturing a semiconductor device comprising: forming a gate insulator on a substrate, the gate insulator including a high-dielectric film in whole or part; forming a first metal film on the gate insulator; forming a second metal film on the first metal film; and forming a reaction film between the gate insulator and the first metal film by letting the high-dielectric film and the first metal film react with each other through a thermal treatment. ### Claim 2 (depends on 1) The method of manufacturing a semiconductor device according to claim 1, wherein at least one of elements included in the first metal film is the same as or congeneric to at least one of elements included in the second metal film. ### Claim 3 (depends on 1) The method of manufacturing a semiconductor device according to claim 1, wherein the first metal film includes at least one of V, Nb, Ta, Ti, Zr and Hf, or at least one compound of one of V, Nb, Ta, Ti, Zr and Hf, and the high-dielectric film includes at least one oxide of one of Hf, Zr, Ti, Ta, Al, Sr, Y and La, at least one oxide of silicon and one of Zr, Ti, Ta, Al, Sr, Y and La, or silicon oxide. ### Claim 4 (depends on 1) The method of manufacturing a semiconductor device according to claim 1, wherein a damage in the high-dielectric film which has occurred at a time of forming the first metal film is compensated by forming the reaction film. ### Claim 5 (depends on 4) The method of manufacturing a semiconductor device according to claim 4, wherein the first metal film includes at least one of V, Nb, Ta, Ti, Zr and Hf, or at least one compound of one of V, Nb, Ta, Ti, Zr and Hf, and the high-dielectric film includes at least one oxide of one of Hf, Zr, Ti, Ta, Al, Sr, Y and La, at least one oxide of silicon and one of Zr, Ti, Ta, Al, Sr, Y and La, or silicon oxide. ### Claim 6 (depends on 4) The method of manufacturing a semiconductor device according to claim 4, wherein at least one of elements included in the first metal film is the same as or congeneric to at least one of elements included in the second metal film. ### Claim 7 (depends on 6) The method of manufacturing a semiconductor device according to claim 6, wherein the first metal film includes at least one of V, Nb, Ta, Ti, Zr and Hf, or at least one compound of one of V, Nb, Ta, Ti, Zr and Hf, and the high-dielectric film includes at least one oxide of one of Hf, Zr, Ti, Ta, Al, Sr, Y and La, at least one oxide of silicon and one of Zr, Ti, Ta, Al, Sr, Y and La, or silicon oxide. ### Claim 8 (depends on 1) The method of manufacturing a semiconductor device according to claim 1, wherein the high-dielectric film includes a hafnium system insulator. ### Claim 9 (depends on 1) The method of manufacturing a semiconductor device according to claim 1, wherein the reaction film is formed by a thermal treatment under a temperature of 900° C. after the first metal film is formed on the gate insulator. ### Claim 10 A semiconductor device comprising: a gate insulator formed on a substrate, the gate insulator including a high-dielectric film in whole or part; a reaction film including a first metal on the gate insulator; and a metal film including a second metal, which is the same as the first metal or congeneric to the first metal, on the reaction film. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the first metal includes at least one of V, Nb, Ta, Ti, Zr and Hf, or at least one compound of one of V, Nb, Ta, Ti, Zr and Hf, and the high-dielectric film includes at least one oxide of one of Hf, Zr, Ti, Ta, Al, Sr, Y and La, at least one oxide of silicon and one of Zr, Ti, Ta, Al, Sr, Y and La, or silicon oxide. ### Claim 12 (depends on 10) The semiconductor device according to claim 10, wherein the high-dielectric film includes a hafnium system insulator. ### Claim 13 (depends on 10) The semiconductor device according to claim 10, wherein the gate insulator in at least a part thereof includes a threshold adjusting film for controlling an operational threshold of the semiconductor device. ### Claim 14 A semiconductor device comprising: a gate insulator formed on a substrate, the gate insulator including a high-dielectric film in whole or part; a reaction film formed as a result of thermal reaction between at least a part of the high-dielectric film and a first metal; and a metal film including a second metal on the reaction film. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein the first metal includes at least one of V, Nb, Ta, Ti, Zr and Hf, or at least one compound of one of V, Nb, Ta, Ti, Zr and Hf, and the high-dielectric film includes at least one oxide of one of Hf, Zr, Ti, Ta, Al, Sr, Y and La, at least one oxide of silicon and one of Zr, Ti, Ta, Al, Sr, Y and La, or silicon oxide. ### Claim 16 (depends on 14) The semiconductor device according to claim 14, wherein a damage in the high-dielectric film which has occurred at a time of forming the first metal film is compensated by forming the reaction film. ### Claim 17 (depends on 16) The semiconductor device according to claim 16, wherein the first metal includes at least one of V, Nb, Ta, Ti, Zr and Hf, or at least one compound of one of V, Nb, Ta, Ti, Zr and Hf, and the high-dielectric film includes at least one oxide of one of Hf, Zr, Ti, Ta, Al, Sr, Y and La, at least one oxide of silicon and one of Zr, Ti, Ta, Al, Sr, Y and La, or silicon oxide. ### Claim 18 (depends on 14) The semiconductor device according to claim 14, wherein the gate insulator in at least a part thereof includes a threshold adjusting film for controlling an operational threshold of the semiconductor device.