# US 2009/0267136 A1 · Semiconductor memory device and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2009/0267136 A1 - Document ID: US20090267136A1 - Status: Published application - Kind: A1 - Application number: 12/498,149 - Filed: 2009-07-06 - Published: 2009-10-29 - Earliest claimed: 2003-10-02 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Akira Goda; Mitsuhiro Noguchi - Web page: https://patentgrep.com/patent/US20090267136A1 ## CPC - H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices - H10B 43/30: characterised by the memory core region - H10B 43/40: characterised by the peripheral circuit region - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor memory device having a memory cell region and a peripheral circuit region, and a method of manufacturing such a semiconductor memory device, are proposed, in which trench grooves are formed to be shallow in the memory cell region in order to improve the yield, and trench grooves are formed to be deep in the high voltage transistor region of the peripheral circuit region, in particular in a high voltage transistor region thereof, in order to improve the element isolation withstand voltage. A plurality of memory cell transistors having an ONO layer 15 serving as a charge accumulating insulating layer are provided in the memory cell region, where element isolation grooves 6 for these memory cell transistors are narrow and shallow. Two types of transistors, one for high voltage and the other for low voltage, having gate insulating layers 16 or 17, which are different from the ONO layer 15 in the memory cell region, are provided in the peripheral circuit region, where at least element isolation grooves 23 for high voltage transistors are wide and deep. In this way, it is possible to improve the degree of integration and yield in the memory cell region, and secure withstand voltage in the peripheral circuit region. ## Claims ### Claim 1 A semiconductor memory device comprising: a first region including a plurality of memory cell transistors, each memory cell transistor employing a first gate insulating layer having a laminated structure including at least a charge accumulating insulating layer; and a second region including a plurality of transistors, each transistor employing a second gate insulating layer which is different from the charge accumulating insulating layer, the first and second regions being formed on a semiconductor substrate, and a depth of an element isolation trench in the first region, measured from a surface of the semiconductor substrate, being set to be shallower than a depth of an element isolation trench in the second region, measured from the surface of the semiconductor substrate. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein a difference between the depth of the element isolation trench in the first region, measured from the surface of the semiconductor substrate, and the depth of the element isolation trench in the second region, measured from the surface of the semiconductor substrate, is set to be 10 nm or more and 150 nm or less. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein a difference between the depth of the element isolation trench in the first region, measured from the surface of the semiconductor substrate, and the depth of the element isolation trench in the second region, measured from the surface of the semiconductor substrate, is set to be larger than a thickness of the charge accumulating insulating layer. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, wherein a boundary at which a depth of an element isolation trench changes between that in the first region and that in the second region is set in a self-aligned manner with respect to a boundary between the first gate insulating layer and the second gate insulating layer. ### Claim 5 (depends on 2) The semiconductor memory device according to claim 2, wherein a boundary at which a depth of an element isolation trench changes between that in the first region and that in the second region is set in a self-aligned manner with respect to a boundary between the first gate insulating layer and the second gate insulating layer. ### Claim 6 (depends on 3) The semiconductor memory device according to claim 3, wherein a boundary at which a depth of an element isolation trench changes between that in the first region and that in the second region is set in a self-aligned manner with respect to a boundary between the first gate insulating layer and the second gate insulating layer. ### Claim 7 A semiconductor memory device comprising: a first region including a plurality of memory cell transistors, each memory cell transistor employing a first gate insulating layer having a laminated structure including at least a charge accumulating insulating layer; a second region including a plurality of transistors, each transistor employing a second gate insulating layer which is different from the charge accumulating insulating layer; and a third region including a plurality of transistors, each transistor employing a third gate insulating layer which is different from the charge accumulating insulating layer, and is thinner than the second gate insulating layer, the first, second and third regions being formed on a semiconductor substrate, and a depth of an element isolation trench in the first region, measured from a surface of the semiconductor substrate, being set to be shallower than a depth of an element isolation trench in the second region, measured from the surface of the semiconductor substrate, and being set to be substantially the same as a depth of an element isolation trench in the third region, measured from the surface of the semiconductor substrate. ### Claim 8 (depends on 7) The semiconductor memory device according to claim 7, wherein: each of gate electrodes in the memory cell transistors, the transistors in the second region, and the transistors in the third regions has a two-layer structure including a first gate electrode formed on the gate insulating layer and a second gate electrode formed on the first gate electrode and electrically connected to the first gate electrode; and in the first and second regions, the second gate electrodes are located on the element isolation trenches so as to contact upper surfaces thereof, and in the third region, the second gate electrodes are located over the element isolation trenches with the first gate electrodes being located therebetween. ### Claim 9 (depends on 7) The semiconductor memory device according to claim 7, wherein a difference between the depth of the element isolation trench in the first region, measured from the surface of the semiconductor substrate, and the depth of the element isolation trench in the second region, measured from the surface of the semiconductor substrate, is set to be 10 nm or more and 150 nm or less. ### Claim 10 (depends on 7) The semiconductor memory device according to claim 7, wherein a difference between the depth of the element isolation trench in the first region, measured from the surface of the semiconductor substrate, and the depth of the element isolation trench in the second region, measured from the surface of the semiconductor substrate, is set to be larger than a thickness of the charge accumulating insulating layer. ### Claim 11 (depends on 7) The semiconductor memory device according to claim 7, wherein a boundary at which a depth of an element isolation trench changes between that in the first region and that in the second region is set in a self-aligned manner with respect to a boundary between the first gate insulating layer and the second gate insulating layer. ### Claim 12 (depends on 8) The semiconductor memory device according to claim 8, wherein a boundary at which a depth of an element isolation trench changes between that in the first region and that in the second region is set in a self-aligned manner with respect to a boundary between the first gate insulating layer and the second gate insulating layer. ### Claim 13 (depends on 9) The semiconductor memory device according to claim 9, wherein a boundary at which a depth of an element isolation trench changes between that in the first region and that in the second region is set in a self-aligned manner with respect to a boundary between the first gate insulating layer and the second gate insulating layer. ### Claim 14 (depends on 10) The semiconductor memory device according to claim 10, wherein a boundary at which a depth of an element isolation trench changes between that in the first region and that in the second region is set in a self-aligned manner with respect to a boundary between the first gate insulating layer and the second gate insulating layer. ### Claim 15 A method of manufacturing a semiconductor memory device comprising: a first region including a plurality of memory cell transistors, each memory cell transistor employing a first gate insulating layer having a laminated structure including at least a charge accumulating insulating layer; and a second region including a plurality of transistors, each transistor employing a second gate insulating layer which is different from the charge accumulating insulating layer, the first and second regions being formed on a semiconductor substrate, the method comprising a step of etching the semiconductor substrate in the second region in order to form a second element isolation trench, using the charge accumulating insulating layer in the first region as an etching stopper, so that the semiconductor substrate in the first region is not etched. ### Claim 16 (depends on 15) The method of manufacturing a semiconductor memory device according to claim 15, wherein after the step of etching the semiconductor substrate in the second region, the first gate insulating layer including the charge accumulating layer in the first region is etched in order to form a first element isolation trench and at the same time the semiconductor substrate in the second region is etched in order to etch the second element isolation trench further, thereby making a depth of the first element isolation trench in the first region, measured from a surface of the semiconductor substrate, shallower than a depth of the second element isolation trench in the second region, measured from the surface of the semiconductor substrate. ### Claim 17 A method of manufacturing a semiconductor memory device comprising: a first region including a plurality of memory cell transistors, each memory cell transistor employing a first gate insulating layer having a laminated structure including at least a charge accumulating insulating layer; a second region including a plurality of transistors, each transistor employing a second gate insulating layer which is different from the charge accumulating insulating layer; and a third region including a plurality of transistors, each transistor employing a third gate insulating layer which is different from the charge accumulating insulating layer, and is thinner than the second gate insulating layer, the first, second and third regions being formed on a semiconductor substrate, wherein: in the first and third regions, at least the first gate insulating layer and a gate electrode formed thereon are located on the semiconductor substrate; in the second region, at least the second gate insulating layer and a gate electrode formed thereon are located on the semiconductor substrate; and the semiconductor substrate is etched in a self-aligned manner with respect to the gate electrodes, thereby forming the element isolation trenches in the first, second and third regions. ### Claim 18 (depends on 17) The method of manufacturing a semiconductor memory device according to claim 17, wherein the element isolation grooves are filled with an insulating material, and then the first gate insulating layer and the gate electrodes in the third region are removed. ### Claim 19 (depends on 18) The method of manufacturing a semiconductor memory device according to claim 18, wherein after the first gate insulating layer and the gate electrodes are removed, the third gate insulating layer is formed on at least the semiconductor substrate in the third region.