Method for designing semiconductor integrated circuit
AssigneeKabushiki Kaisha Toshiba
InventorFumiyuki YAMANE
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Abstract
A method for designing a semiconductor integrated circuit, includes: disposing a plurality of cells in a cell layout region on the basis of a net list indicating connection relations of the plurality of cells to satisfy a setup timing condition; generating a plurality of power regions dividing the cell layout region into plurality; calculating a consumption current of each of the power regions by using a cell power file indicating a consumption current of each of the cells; adjusting layout positions of the temporarily disposed cells with reference to the consumption current of each of the power regions in a range that the setup timing condition is not violated; and optimizing hold timing of the cells after the position adjustment of the cells.
Claims20
A method for designing a semiconductor integrated circuit, comprising:
- disposing a plurality of cells in a cell layout region on the basis of a net list indicating connection relations of the plurality of cells to satisfy a setup timing condition;
- generating a plurality of power regions dividing the cell layout region into plurality;
- calculating a consumption current of each of the power regions by using a cell power file indicating a consumption current of each of the cells;
- adjusting layout positions of the temporarily disposed cells with reference to the consumption current of each of the power regions in a range that the setup timing condition is not violated;
- and
- optimizing hold timing of the cells after the position adjustment of the cells.
A method for designing a semiconductor integrated circuit, comprising:
- temporarily disposing a plurality of cells in a cell layout region on the basis of a net list indicating connection relations of the plurality of cells to satisfy a setup timing condition and a hold timing condition;
- generating a plurality of power regions dividing the cell layout region into plurality;
- calculating a consumption current of each of the power regions by using a cell power file indicating a consumption current of each of the cells;
- and
- adjusting layout positions of the temporarily disposed cells with reference to the consumption current of each of the power regions in a range that the setup timing condition and the hold timing condition are not violated.
Dependencies are inferred from the claim text.