High-Speed Video Serializer and Deserializer
OwnerTarun Setya, Cristian Samoila +1inventors
InventorsTarun Setya, Cristian Samoila, Poupak Khodabandeh
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Abstract
A high-speed video serializer has an X bit parallel input bus and a Y bit parallel output bus, where X and Y are multiples of one another (e.g., 2). A multiplexer is connected between the input bus and the output bus and is operated such that a frequency of the signals on the output bus is a multiple of the frequency of the signals on the input bus. A circuit provides a clock signal substantially in sync with the signals on the output bus. A high speed video deserializer is also disclosed as are methods of operating the serializer and deserializer.
Claims17
A high-speed video serializer, comprising:
- an X bit parallel input bus and a Y bit parallel output bus, where X and Y are multiples of one another;
- a multiplexer connected between said input bus and said output bus, said multiplexer operated such that a frequency of the signals on said output bus is a multiple of the frequency of the signals on said input bus;
- and
- a circuit for providing a clock signal substantially in sync with the signals on said output bus.
A method of operating a high-speed video serializer, comprising:
- multiplexing a signal on an X bit parallel input bus onto a Y bit parallel output bus such that a frequency of the signal on said output bus is a multiple of a frequency of the signal on said input bus;
- and
- generating a clock signal substantially in sync with the signal on said output bus.
A high-speed video deserializer, comprising:
- an X bit parallel input bus responsive to received data signals and a Y bit parallel output bus, where X and Y are multiples of one another;
- a circuit for receiving and providing a sampling clock substantially in sync with the signal on said input bus;
- a splitter responsive to said input bus;
- a first data sampling circuit responsive to said splitter for detecting data on a positive edge of said sampling clock;
- and
- a second data sampling circuit responsive to said splitter for detecting data on a negative edge of said sampling clock, and wherein said Y bit parallel output bus is responsive to said first and second data sampling circuits.
A method of operating a high-speed video deserializer, comprising:
- receiving data signals at an X bit parallel input bus and receiving a sampling clock;
- delaying said received sampling clock by a programmable amount to produce a clock signal substantially in sync with the signal on said input bus;
- splitting said X bit parallel input bus into two X bit input buses;
- detecting data on a positive edge of said sampling clock in one of said two X bit input buses;
- and
- detecting data on a negative edge of said sampling clock in the other of said two X bit input buses, and wherein a Y bit parallel output bus is responsive to said data detecting, and wherein X and Y are multiples of one another.
Dependencies are inferred from the claim text.