Processor for performing multiply-add operations on packed data

A microprocessor comprising:

• a decoder to receive a multiply-add instruction having an opcode format comprising three bytes, a third byte of the three bytes permitting a source register address and a source-destination register address each one of the source register address and the source-destination register address consisting of three bits;
• a register file to initially store, in a first register corresponding to the source-destination register address, a first 64-bit packed data having a first plurality of packed data elements including an A1, an A2, an A3, and an A4 initial data element;
• said register file also to store, in a second register corresponding to the source register address, a second 64-bit packed data having a second plurality of packed data elements including a B1, a B2, a B3, and a B4 initial data element, wherein each initial data element in said first plurality of data elements corresponds to an initial data element in said second plurality of data elements, in a respective position;
• a circuit coupled to said register file and said decoder, said circuit in response to the multiply-add instruction to,
• multiply together only said corresponding initial data elements in said first and second packed data to generate corresponding intermediate data elements including at least A1*B1, A2*B2, A3*B3, A4*B4 intermediate data elements, said intermediate data elements being paired into a plurality of sets, arithmetically combine the intermediate data elements in each of said plurality of sets to generate a plurality of result data elements respectively representing the addition of paired intermediate data elements including at least (A1*B1+A2*B2) and (A3*B3+A4*B4) result data elements, wherein each of said plurality of result data elements provides a higher precision than said initial data elements, and store as a result of executing the multiply-add instruction said plurality of result data elements in the first register of said register file as a third 64-bit packed data, wherein each element in the third packed data is the result of a multiply-add operation on two pairs of corresponding initial data elements.