DLL circuit with wide-frequency locking range and error-locking-avoiding function
AssigneeEtron Technology, Inc.
InventorHsien-Sheng Huang
Life of this patent
Estimating the term…
Abstract
A delay-locked loop (DLL) circuit. In the evaluation period, the DLL circuit adjusts needed delay period of time for a reference clock signal by adjusting the amount of the used delay units which each of has fixed delay period of time digitally and controlling the delay period of time of the voltage control delay circuit analogically. In the locking period, the DLL circuit utilizes the delay time of the delay units, which is decided in the evaluation period, along with the voltage control delay circuit, to lock phase of the reference clock signal. In this way, the stability of the delay period of time of the voltage control delay circuit increases.
Claims15
A delay-locked loop circuit with wide frequency locking range and error-locking avoiding function, for generating a delayed locking periodic signal according to a reference periodic signal, the delay-locked loop circuit comprising:
- a phase/frequency detector, comprising;
- a first input terminal, for receiving the reference periodic signal;
- a second input terminal;
- a first output terminal, wherein the phase/frequency detector outputs a first controlling signal via the first output terminal of the phase/frequency detector according to signals at the first input terminal and the second input terminal of the phase/frequency detector;
- and
- a second output terminal, wherein the phase/frequency detector outputs a second controlling signal via the second output terminal of the phase/frequency detector according to signals at the first input terminal and the second input terminal of the phase/frequency detector;
- a voltage controller, coupled to the first and the second output terminals of the phase/frequency detector, the voltage controller outputs a corresponded voltage level according to the first controlling signal or the second controlling signal;
- a voltage controlled delay circuit, comprising:
- an input terminal, for receiving the reference periodic signal;
- a control terminal, coupled to the output terminal of the voltage controller;
- and
- an output terminal, wherein the voltage controlled delay circuit delays the received reference periodic signal according to the corresponded level voltage outputted from the voltage controller;
- a predetermined delay circuit, for delaying a received signal for a first predetermined time, an output terminal of the predetermined delay circuit being coupled to the second input terminal of the phase/frequency detector;
- an adjustable delay circuit, for adjusting a delay time of the adjustable delay circuit;
- a first switch, comprising:
- a first terminal, coupled to the output terminal of the voltage controlled delay circuit;
- a second terminal, coupled to an input terminal of the predetermined delay circuit;
- a third terminal, coupled to an input terminal of the adjustable delay circuit;
- and
- a control terminal, for coupling the first terminal of the first switch to the second terminal or the third terminal of the first switch according to signals received at the control terminal of the first switch;
- a second switch, comprising:
- a first terminal, for outputting the delayed locking periodic signal;
- a second terminal, coupled to the output terminal of the predetermined delay circuit;
- a third terminal, coupled to an output terminal of the adjustable delay circuit;
- and
- a control terminal, for coupling the first terminal of the second switch to the second terminal or the third terminal of the second switch according to signals received at the control terminal of the second switch;
- and
- a third switch, comprising:
- a first terminal, coupled to the first terminal of the second switch;
- a second terminal, coupled to the input terminal of the adjustable delay circuit;
- a third terminal, coupled to the input terminal of the predetermined delay circuit;
- and
- a control terminal, for coupling the first terminal of the third switch to the second terminal or the third terminal of the third switch according to signals received at the control terminal of the third switch.
Dependencies are inferred from the claim text.