Nonvolatile Memory Cell and Data Latch Incorporating Nonvolatile Memory Cell

Abstract

A nonvolatile memory cell, comprising: a first NMOS transistor having a floating gate; a second NMOS transistor and a third NMOS transistor connected to a drain side and a source side of the first NMOS transistor; and a first PMOS transistor and a second PMOS transistor each having the floating gate as a gate, and wherein a read signal is inputted to gates of the second and third NMOS transistors, a control gate signal is inputted to a source and an n-well of the first PMOS transistor, an erase signal is inputted to a source and an n-well of the second PMOS transistor, and a write data signal is inputted to a source of the first NMOS transistor.

Dependencies are inferred from the claim text.