# US 2009/0261997 A1 · Multi-Speed Burst Mode Serializer/De-Serializer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2009/0261997 A1 - Document ID: US20090261997A1 - Status: Published application - Kind: A1 - Application number: 12/488,774 - Filed: 2009-06-22 - Published: 2009-10-22 - Earliest claimed: 2007-12-05 - Assignees: Broadcom Corporation - Inventors: Wael William Diab - Web page: https://patentgrep.com/patent/US20090261997A1 ## CPC - H04J 3/0685: {Clock or time synchronisation in a node; Intranode synchronisation} - H04J 3/047: {Distributors with transistors or integrated circuits} - H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S) ## Abstract A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds. These various modes of operation can enable a single SerDes design to apply to a variety of speeds and network configurations (e.g., point-to-point or point-to-multipoint). In one example, the design can be initially configured for operation with a single ONT or a network of ONTs at a single speed, or can be dynamically configured during operation for use with a network of ONTs operating at different speeds. ## Claims ### Claim 1 A multi-speed serializer/de-serializer transceiver, comprising: a clock recovery module for use in a point-to-multipoint network that is configurable in real time to operate in a plurality of modes in receiving communication from a first and a second optical network unit in said point-to-multipoint network; and configuration registers that store a first parameter for the configuration of said clock recovery module in a first mode that enables clock recovery from a signal received from said first optical network unit at a first speed, and a second parameter for the configuration of said clock recovery module in a second mode that enables clock recovery from a signal received from said second optical network unit at a second speed different from said first speed. ### Claim 2 (depends on 1) The multi-speed serializer/de-serializer transceiver of claim 1, wherein said clock recovery module includes a phase locked loop. ### Claim 3 (depends on 1) The multi-speed serializer/de-serializer transceiver of claim 1, wherein said clock recovery module includes a delay locked loop. ### Claim 4 (depends on 1) The multi-speed serializer/de-serializer transceiver of claim 1, wherein communication from said first optical network unit and said second optical network unit are received on different time slots. ### Claim 5 (depends on 1) The multi-speed serializer/de-serializer transceiver of claim 1, wherein a selected mode of said clock recovery module is based on a speed indication of a received signal. ### Claim 6 (depends on 5) The multi-speed serializer/de-serializer transceiver of claim 5, is provided through one or more external pins to the multi-speed serializer/de-serializer transceiver. ### Claim 7 (depends on 5) The multi-speed serializer/de-serializer transceiver of claim 5, wherein said speed indication is provided through an EPROM. ### Claim 8 (depends on 5) The multi-speed serializer/de-serializer transceiver of claim 5, wherein said speed indication is provided through in-band communication to the multi-speed serializer/de-serializer transceiver. ### Claim 9 A multi-speed serializer/de-serializer, comprising: a clock recovery module that is configurable in real time to operate in a plurality of modes, wherein a first of said plurality of modes is capable of locking onto an incoming embedded clock within signals generated by a first optical network unit at a first speed, and a second of said plurality of modes is capable of locking onto an incoming embedded clock within signals generated by a second optical network unit at a second speed different from said first speed, wherein said clock recovery module is configured to operate in one of said plurality for each time slot based on a speed indication for each time slot. ### Claim 10 (depends on 9) The multi-speed serializer/de-serializer of claim 9, further comprising configurable registers that store parameters for said first mode and said second mode. ### Claim 11 (depends on 10) The multi-speed serializer/de-serializer of claim 10, wherein said parameters are values for a clock multiplier/divider. ### Claim 12 (depends on 9) The multi-speed serializer/de-serializer of claim 9, wherein said clock recovery module includes a phase locked loop. ### Claim 13 (depends on 9) The multi-speed serializer/de-serializer of claim 9, wherein said clock recovery module includes a delay locked loop. ### Claim 14 (depends on 9) The multi-speed serializer/de-serializer of claim 9, wherein said speed indication is provided through one or more external pins to the multi-speed serializer/de-serializer transceiver. ### Claim 15 (depends on 9) The multi-speed serializer/de-serializer of claim 9, wherein said speed indication is provided through an EPROM. ### Claim 16 (depends on 9) The multi-speed serializer/de-serializer of claim 9, wherein said speed indication is provided through in-band communication to the multi-speed serializer/de-serializer transceiver. ### Claim 17 A multi-speed serializer/de-serializer method, comprising: configuring a clock recovery module of a serializer/de-serializer in a first operating mode that locks onto an incoming embedded clock within a first signal generated by a first optical network unit operating at a first operating speed; and reconfiguring, in real time, said clock recovery module to change from said first operating mode to a second operating mode that locks onto an incoming embedded clock within a second signal generated by a second optical network unit operating at a second operating speed different from said first operating speed. ### Claim 18 (depends on 17) The method of claim 17, wherein said configuring and reconfiguring comprises configuring a phase locked loop. ### Claim 19 (depends on 17) The method of claim 17, wherein said configuring and reconfiguring comprises configuring a delay locked loop. ### Claim 20 (depends on 17) The method of claim 17, wherein said configuring and reconfiguring comprises configuring a clock multiplier/divider. ### Claim 21 (depends on 17) The method of claim 17, further comprising identifying an operating speed based on an assigned time slot.