# US 2009/0261402 A1 · Method and structure for a semiconductor charge storage device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2009/0261402 A1 - Document ID: US20090261402A1 - Status: Published application - Kind: A1 - Application number: 12/106,096 - Filed: 2008-04-18 - Published: 2009-10-22 - Earliest claimed: 2008-04-18 - Assignees: Macronix International Co., Ltd. - Inventors: Chao-I Wu - Web page: https://patentgrep.com/patent/US20090261402A1 ## CPC - H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors - H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes} - H10D 64/037: {comprising charge-trapping insulators} - H10D 64/685: {being perpendicular to the channel plane} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor charge storage device includes a semiconductor substrate having a surface region. The semiconductor substrate is characterized by a first conductivity type. A charge trapping material overlies and is in contact with at least a portion of the surface region of the semiconductor substrate. The charge trapping material is characterized by a first dielectric constant and by a first charge trapping capability. The first dielectric constant is higher than a dielectric constant associated with silicon oxide. A dielectric material overlies and is in contact with at least a portion of the charge trapping material. The dielectric material is formed using a conversion of a portion of the charge trapping material for providing a second charge trapping capability. The device also includes a conductive material overlying the second dielectric. The conductive material is capable of receiving an electrical signal to cause electrical charges being trapped in the semiconductor charge storage device. ## Claims ### Claim 1 A charge storage device comprising: a semiconductor substrate having a surface region; a charge trapping material overlying the surface region of the semiconductor substrate, the charge trapping material being characterized by a first dielectric constant which is higher than a dielectric constant associated with silicon oxide, the charge trapping material being also characterized by a first charge trapping capability; a dielectric material being formed by converting a portion of the charge trapping material, the charge trapping material and the dielectric material forming a composite dielectric characterized by a second charge trapping capability, the second charge trapping capability being higher than the first charge trapping capability; and a conductive material overlying the dielectric material, the conductive material being capable of receiving an electrical signal to cause electrical charges being trapped in the charge storage device. ### Claim 2 (depends on 1) The charge storage device of claim 1 wherein the semiconductor substrate comprises silicon. ### Claim 3 (depends on 1) The charge storage device of claim 1 wherein the charge trapping material comprises silicon nitride. ### Claim 4 (depends on 1) The charge storage device of claim 1 wherein the charge trapping material is selected from a group consisting of HfO2, HfSiO, Al2O3, and ZrO2. ### Claim 5 (depends on 1) The charge storage device of claim 1 wherein the dielectric material comprises silicon oxide. ### Claim 6 (depends on 1) The charge storage device of claim 1 wherein the second charge trapping capability enables an additional threshold voltage shift of more than 1.0 volts in the device as compared with the first charge trapping capability. ### Claim 7 (depends on 1) The charge storage device of claim 1 wherein the charge trapping material is in contact with a portion of the surface region of the semiconductor substrate, the portion of the surface region comprises bare semiconductor surface. ### Claim 8 (depends on 1) The charge storage device of claim 1 wherein the surface region of the semiconductor substrate comprises a layer of native oxide. ### Claim 9 (depends on 1) The charge storage device of claim 1 wherein the surface region of the semiconductor substrate comprises a layer of silicon oxide, the layer of silicon oxide being characterized by a thickness selected to allow charge tunneling and relatively low charge retention capability. ### Claim 10 (depends on 1) The charge storage device of claim 1 further comprising: a source region characterized by a second conductivity type; a drain region characterized by the second conductivity type; a channel region of the first conductivity type sandwiched between the source region and the drain region, the channel region including a portion of the surface region of the semiconductor substrate; and a gate electrode, the gate electrode including the conductive material. ### Claim 11 (depends on 1) The charge storage device of claim 1 wherein converting the portion of the charge trapping material includes oxidizing the portion of the charge trapping material. ### Claim 12 A method for forming a semiconductor charge storage device, the method comprising: providing a semiconductor substrate having a surface region; forming a charge trapping material overlying the surface region of the semiconductor substrate, the charge trapping material being characterized by a first dielectric constant which is higher than a dielectric constant associated with silicon oxide, the charge trapping material also being characterized by a first charge trapping capability; converting a portion of the charge trapping material to form a dielectric material for providing a second charge trapping capability; and forming a conductive material over the dielectric material, the conductive material being capable of receiving an electrical signal to cause electrical charges being trapped in the semiconductor charge storage device. ### Claim 13 (depends on 12) The method of claim 12 wherein the semiconductor substrate comprises silicon. ### Claim 14 (depends on 12) The method of claim 12 where in the charge trapping material comprises silicon nitride. ### Claim 15 (depends on 12) The method of claim 12 wherein converting the top portion of the charge trapping material comprises partially oxidizing the charge trapping material in a thermal process. ### Claim 16 (depends on 12) The method of claim 12 wherein the charge trapping material is selected from a group consisting of HfO2, HfiO, Al2O3, and ZrO2. ### Claim 17 (depends on 12) The method of claim 12 wherein the surface region of the semiconductor substrate comprises a layer of silicon oxide, the layer of silicon oxide being characterized by a thickness selected to allow charge tunneling. ### Claim 18 (depends on 12) The method of claim 12 further comprising: providing a source region in the semiconductor substrate, the source region being characterized by a second conductivity type; providing a drain region in the semiconductor substrate, the drain region being characterized by the second conductivity type; providing a channel region of the first conductivity type sandwiched between the source region and the drain region, the channel region including a portion of the surface region of the semiconductor substrate; and providing a gate electrode, the gate electrode including the conductive material. ### Claim 19 (depends on 12) The method of claim 12 wherein converting the portion of the charge trapping material includes oxidizing the portion of the charge trapping material. ### Claim 20 A method for forming a semiconductor charge storage device, the method comprising: forming a charge trapping material overlying a surface region of a semiconductor substrate, the charge trapping material being characterized by a first dielectric constant which is higher than a dielectric constant associated with silicon oxide, the charge trapping material also being characterized by a first charge trapping capability; partially converting a predetermined thickness of the charge trapping material to form a dielectric material, the dielectric material and the remaining charge trapping material having a second charge trapping capability; and forming a conductive material over the dielectric material, the conductive material being coupled to a voltage to cause electrical charges being trapped in the dielectric material and the remaining charge trapping material. ### Claim 21 (depends on 20) The method of claim 20 wherein the second charge trapping capability enables an additional threshold voltage shift of more than 1.0 volts in the device over the first charge trapping capability. ### Claim 22 (depends on 20) The method of claim 20 wherein the charge trapping material is in contact with a portion of the surface region of the semiconductor substrate, the portion of the surface region comprises bare silicon surface. ### Claim 23 (depends on 20) The method of claim 20 wherein the surface region of the semiconductor substrate comprises a layer of native oxide. ### Claim 24 (depends on 20) The method of claim 20 wherein the surface region of the semiconductor substrate comprises a layer of silicon oxide, the layer of silicon oxide being characterized by a thickness selected to allow charge tunneling and relatively low charge retention capability. ### Claim 25 (depends on 20) The method of claim 20 wherein partially converting a predetermined thickness of the charge trapping material includes partially oxidizing the predetermined thickness of the charge trapping material.