# US 2009/0260864 A1 · Circuit board and semiconductor integrated circuit module including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2009/0260864 A1 - Document ID: US20090260864A1 - Status: Published application - Kind: A1 - Application number: 12/346,655 - Filed: 2008-12-30 - Published: 2009-10-22 - Earliest claimed: 2008-04-16 - Assignees: Hynix Semiconductor Inc. - Inventors: Jun Ho Lee - Web page: https://patentgrep.com/patent/US20090260864A1 ## CPC - H05K 1/0245: {Lay-out of balanced signal pairs, e.g. differential lines or twisted lines} - H05K 1/0236: {Electromagnetic band-gap structures} - H05K 2201/09236: Parallel layout - H05K 2201/09309: Core having two or more power planes; Capacitive laminate of two power planes - H05K 2201/09663: Divided layout, i.e. conductors divided in two or more parts - H05K 2201/09681: Mesh conductors, e.g. as a ground plane - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A circuit board includes a plurality of differential signal line pairs, and a plurality of electromagnetic bandgap (EBG) patterns, each configured to be disposed to overlap the plurality of differential signal line pairs, wherein the EBG patterns are electrically insulated from the differential signal line pairs. ## Claims ### Claim 1 A circuit board, comprising: a plurality of differential signal line pairs; and a plurality of electromagnetic bandgap (EBG) patterns, each configured to be disposed to overlap the plurality of differential signal line pairs, wherein the EBG patterns are electrically insulated from the differential signal line pairs. ### Claim 2 (depends on 1) The circuit board of claim 1, further comprising a plurality of insulating layers, each configured to be interposed between the plurality of differential signal line pairs and the plurality of EBG patterns. ### Claim 3 (depends on 2) The circuit board of claim 2, wherein an uppermost one of the plurality of EBG patterns is provided within a second one of the plurality of insulating layers and spaced apart from one of the plurality of differential signal line pairs by a first one of the plurality of insulating layer. ### Claim 4 (depends on 3) The circuit board of claim 3, wherein the uppermost one of the plurality of EBG patterns is provided along an interface between the second one of the plurality of insulating layers and the first one of the plurality of insulating layers. ### Claim 5 (depends on 2) The circuit board of claim 2, wherein an lowermost one of the plurality of EBG patterns is provided within a next to last one of the plurality of insulating layers and spaced apart from a second one of the plurality of differential signal line pairs by a last one of the plurality of insulating layer. ### Claim 6 (depends on 5) The circuit board of claim 5, wherein the lowermost one of the plurality of EBG patterns is provided along an interface between the next to last one of the plurality of insulating layers and the last one of the plurality of insulating layers. ### Claim 7 (depends on 1) The circuit board of claim 1, further comprising a plurality of signal line layers configured to include the plurality of differential signal line pairs. ### Claim 8 (depends on 1) The circuit board of claim 1, further comprising a plurality of power supply layers configured to include the plurality of EBG patterns. ### Claim 9 (depends on 8) The circuit board of claim 8, wherein an uppermost one of the plurality of EBG patterns is provided along an interface between an uppermost one of the plurality of insulating layers and an uppermost one of the plurality of power supply layers adjacent to an uppermost one of the plurality of differential signal line pairs. ### Claim 10 (depends on 9) The circuit board of claim 9, wherein a lowermost one of the plurality of EBG patterns 80 is provided along an interface between a lowermost one of the plurality of insulating layers and a lowermost one of the plurality of power supply layers adjacent to a lowermost one of the plurality of differential signal line pairs. ### Claim 11 (depends on 1) The circuit board of claim 1, wherein each of the plurality of EBG patterns are configured to have a width that is about two to about six times wider than a total length of a gap between signal lines of each of the plurality of differential signal line pairs and a line width of each of the plurality of differential signal line pairs. ### Claim 12 (depends on 11) The circuit board of claim 11, wherein each of the plurality of EBG patterns are configured to have a width that is about three times wider than the line width of each of the plurality of differential signal line pairs. ### Claim 13 (depends on 1) The circuit board of claim 1, wherein each of the plurality of EBG patterns include conductive material. ### Claim 14 (depends on 13) The circuit board of claim 13, wherein each of the plurality of EBG patterns include copper. ### Claim 15 A circuit board, comprising: a plurality of signal line layers configured to include a plurality of differential signal line pairs that provide differential signal pairs to a semiconductor integrated circuit chip; a plurality of electromagnetic bandgap (EBG) patterns configured to be disposed adjacent to each of the plurality of differential signal line pairs; and a plurality of insulating layers configured to be disposed between the plurality of signal line layers and the plurality of EBG patterns. ### Claim 16 (depends on 15) The circuit board of claim 15, wherein an uppermost one of the plurality of EBG patterns is provided within a second one of the plurality of insulating layers and spaced apart from an uppermost one of the plurality of differential signal line pairs by a first one of the plurality of insulating layers. ### Claim 17 (depends on 16) The circuit board of claim 16, wherein the uppermost one of the plurality of EBG patterns is provided along an interface between the second one of the plurality of insulating layers and the first one of the plurality of insulating layers. ### Claim 18 (depends on 15) The circuit board of claim 15, wherein an lowermost one of the plurality of EBG patterns is provided within a next to last one of the plurality of insulating layers and spaced apart from a lowermost one of the plurality of differential signal line pairs by a last one of the plurality of insulating layers. ### Claim 19 (depends on 18) The circuit board of claim 18, wherein the lowermost one of the plurality of EBG patterns is provided along an interface between the next to last one of the plurality of insulating layers and the last one of the plurality of insulating layers. ### Claim 20 (depends on 15) The circuit board of claim 15, further comprising a plurality of power supply layers that supply power to the semiconductor integrated circuit chip. ### Claim 21 (depends on 20) The circuit board of claim 20, wherein each of the plurality of EBG patterns are configured to be provided in the plurality of power supply layers. ### Claim 22 (depends on 21) The circuit board of claim 21, wherein an uppermost one of the plurality of EBG patterns is provided along an interface between an uppermost one of the plurality of insulating layers and an uppermost one of the plurality of power supply layers adjacent to an uppermost one of the plurality of differential signal line pairs. ### Claim 23 (depends on 22) The circuit board of claim 22, wherein a lowermost one of the plurality of EBG patterns is provided along an interface between a lowermost one of the plurality of insulating layers and a lowermost one of the plurality of power supply layers adjacent to a lowermost one of the plurality of differential signal line pairs. ### Claim 24 (depends on 15) The circuit board of claim 15, wherein each of the plurality of EBG patterns are configured to have a width that is about two to about six times wider than a total length of a gap between signal lines of each of the plurality of differential signal line pairs and a line width of each of the plurality of differential signal line pairs. ### Claim 25 (depends on 24) The circuit board of claim 24, wherein each of the plurality of EBG patterns are configured to have a width that is about three times wider than the line width of each of the plurality of differential signal line pairs. ### Claim 26 (depends on 15) The circuit board of claim 15, wherein each of the plurality of EBG patterns include conductive material. ### Claim 27 (depends on 26) The circuit board of claim 26, wherein each of the plurality of EBG patterns include copper. ### Claim 28 A semiconductor integrated circuit module, comprising: a circuit board; a memory control device configured to be mounted on the circuit board, and to generate and to output a plurality of differential signal pairs; a plurality of differential signal line pairs, each configured to be formed on the circuit board and to transmit a pair of the plurality of differential signal pairs; a semiconductor memory device configured to be mounted on the circuit board and to be supplied with the plurality of differential signal pairs transmitted along the plurality of differential signal line pairs; and a plurality of electromagnetic bandgap (EBG) patterns, each configured to be disposed in the circuit board and disposed at locations overlapping the plurality of differential signal line pairs. ### Claim 29 (depends on 28) The semiconductor integrated circuit module of claim 28, wherein each of the plurality of EBG patterns are configured to have a width that is about two to about six times wider than a total length of a gap between signal lines of each of the plurality of differential signal line pairs and a line width of each of the plurality of differential signal line pairs. ### Claim 30 (depends on 29) The semiconductor integrated circuit module of claim 29, wherein each of the plurality of EBG patterns are configured to have a width that is about three times wider than the line width of each of the plurality of differential signal line pairs. ### Claim 31 (depends on 28) The semiconductor integrated circuit module of claim 28, wherein each of the plurality of EBG patterns include conductive material. ### Claim 32 (depends on 31) The semiconductor integrated circuit module of claim 31, wherein each of the plurality of EBG patterns include copper. ### Claim 33 (depends on 28) The semiconductor integrated circuit module of claim 28, wherein each of the plurality of differential signal pairs is configured to include at least one of a clock signal pair, a data signal pair, a command signal pair, and an address signal pair. ### Claim 34 A semiconductor integrated circuit module, comprising: a plurality of differential signal line pairs, each configured to transmit differential signal pairs; an input buffer configured to compare the differential signal pairs transmitted from each of the plurality of differential signal line pairs and to perform a buffering operation of signals of the differential signal pairs; and a board configured to include a plurality of electromagnetic bandgap (EBG) patterns, wherein the plurality of differential signal line pairs are disposed on a first side of the board and the EBG patterns are provided on a second side of the board. ### Claim 35 (depends on 34) The semiconductor integrated circuit module of claim 34, wherein each of the plurality of EBG patterns are configured to have a width that is about two to about six times wider than a total length of a gap between signal lines of each of the plurality of differential signal line pairs and a line width of each of the plurality of differential signal line pairs. ### Claim 36 (depends on 35) The semiconductor integrated circuit module of claim 35, wherein each of the plurality of EBG patterns are configured to have a width that is about three times wider than the line width of each of the plurality of differential signal line pairs. ### Claim 37 (depends on 34) The semiconductor integrated circuit module of claim 34, wherein each of the plurality of EBG patterns include conductive material. ### Claim 38 (depends on 37) The semiconductor integrated circuit module of claim 37, wherein each of the plurality of EBG patterns include copper. ### Claim 39 (depends on 34) The semiconductor integrated circuit module of claim 34, wherein the differential signal pairs is configured to include at least one of a clock signal pair, a data signal pair, a command signal pair, and an address signal pair.