Dual loop clock recovery circuit
AssigneeRambus Inc.
InventorsWilliam P. Evans, Eric Naviasky
Life of this patent
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Abstract
A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.
Claims1
A clock recovery circuit comprising:
- (a) a data signal input;
- (b) a clock signal input;
- (c) first and second phase shifters, the phase shifters being connected in series to a reference clock signal input for providing as a recovered clock signal a phase-shifted replica of an input clock signal applied at the clock signal input;
- (d) one or more phase detectors operative to detect a phase difference between a data signal applied at the data signal input and the recovered clock signal and provide one or more phase difference signals representing the phase difference;
- and
- (e) one or more loop filters connected to the phase detector, the loop filters being responsive to the one or more phase difference signals to provide one or more control signals to the phase shifters, the phase shifters being responsive to the one or more control signals.
Dependencies are inferred from the claim text.