US 2009/0257537 A1 · DATA RECOVERY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS THAT MINIMIZES JITTER DURING DATA TRANSMISSION

Abstract

A data recovery circuit that minimizes jitter during data transmission is presented. The data recovery circuit includes a data dividing unit, a data sampling unit, a data selecting unit, and a data recovery unit. The data dividing unit is for dividing external data to generate multiple-division data. The data sampling unit is for sampling the multiple-division data at a first time and a second time to generate sampling data. The data selecting unit is for selecting one of the data sampled at the first time or the second time from the sampling data in accordance to whether the sampling data is transited to output the selected one as selection data. The data recovery unit is for recovering the selection data to internal data in the same logic level as the logic level of the external data.

Claims22

Dependent claims

A data recovery circuit of a semiconductor memory apparatus, comprising:

a data dividing unit configured to generate multiple-division data by dividing external data;
a data sampling unit configured to generate sampling data by sampling the multiple-division data at a first time and at a second time;
a data selecting unit configured to select and to transit one of the sampling data at the first time or at the second time from the sampling data as a selection data;
and
a data recovery unit for recovering the selection data into a logic level of in an internal data to match that of the external data.

2 more elements

A data recovery circuit of a semiconductor memory apparatus, comprising:

a data dividing unit configured to generate first division data and second division data by dividing external data;
a data sampling unit for sampling the first division data at a first time and a second time to generate first sampling data and second sampling data and for sampling the second division data at the first time and the second time to generate third sampling data and fourth sampling data;
a data selecting unit for determining whether the first division data is transited to selectively output the first sampling data or the second sampling data as a first selection data and for determining whether the second division data is transited to selectively output the third sampling data or the fourth sampling data as a second selection data;
and
a data recovery unit for combining the first selection data with the second selection data to recover a combined data to internal data having a logic level identical to that of the external data.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

12/344,736Filed 29 Dec 2008

Priority

KR 10-2008-003299610 Apr 2008

Published

15 Oct 2009

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

H04L 7/0338
Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals: the correction…
G11C 7/1012
Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor: data reordering during…
G11C 7/1051
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data output circuits, e.g. read-out amplifiers,…
G11C 7/1066
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: output…

Data recovery circuit of semiconductor memory apparatus that minimizes jitter during data transmission

Life of this patent

Data recovery circuit of semiconductor memory apparatus that minimizes jitter during data transmission

Life of this patent

Abstract

Claims22