Semiconductor memory device
AssigneePanasonic Corporation
InventorKazuyuki KOUNO
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a selector line selection circuit for selecting, in a read operation, a selector line for connecting a first main bit line connected to the sense amplifier with a sub-bit line to which the memory cell being read is connected, a selector line for connecting the first main bit line with a sub-bit line of at least one sector different from the sector to which the memory cell being read belongs, a selector line for connecting a second main bit line connected to the sense amplifier with a sub-bit line to which the reference cell is connected, and a selector line for connecting the second main bit line with a sub-bit line of at least one sector different from the sector to which the memory cell being read belongs.
Claims7
1-18. (canceled)
A semiconductor memory device, comprising:
- a memory cell array being a virtual ground array and including a plurality of memory cells arranged in a row direction and in a column direction to thereby form a matrix pattern, the memory cell array being divided into a plurality of sectors;
- a plurality of word lines each provided for one row of memory cells;
- a plurality of main bit lines extending in the column direction;
- a plurality of sub-bit lines extending in the column direction and each provided within a sector;
- a plurality of selection transistors corresponding to the sub-bit lines for electrically controlling connections between the main bit lines and the sub-bit lines;
- a plurality of selector lines for controlling a conductivity state of the selection transistors;
- a reference cell for producing a reference voltage used in a read operation;
- a sense amplifier, to which the main bit lines are connected, for determining readout data;
- a word line selection circuit for selecting a word line to which one of the memory cells that is being read is connected and a word line to which the reference cell is connected;
- and
- a selector line selection circuit for selecting, in a read operation,
- a selector line for connecting a first pair of main bit lines with a pair of sub-bit lines to which the memory cell being read is connected,
- a selector line for connecting one of the first pair of main bit lines that is connected to the sense amplifier with a sub-bit line of at least one sector different from a sector to which the memory cell being read belongs,
- a selector line for connecting a second pair of main bit lines with a pair of sub-bit lines to which the reference cell is connected, and
- a selector line for connecting one of the second pair of main bit lines that is connected to the sense amplifier with a sub-bit line of at least one sector different from the sector to which the memory cell being read belongs.
Dependencies are inferred from the claim text.