Semiconductor memory apparatus
AssigneeHynix Semiconductor Inc.
InventorGeun Il Lee
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus includes an input buffering block configured to buffer an input signal transmitted from an input pin, a latch block configured to latch the input signal buffered by the input buffering block, a defect discriminating block configured to discriminate whether or not the input signal latched by the latch block is defective signal in response to a test mode signal, and a data output buffer configured to buffer an output signal of the defect discriminating block to transmit it to a data output pin, wherein the input signal is one of an input command signal and an input address signal.
Claims18
A semiconductor memory apparatus, comprising:
- an input buffering block configured to buffer an input signal transmitted from an input pin;
- a latch block configured to latch the input signal buffered by the input buffering block;
- a defect discriminating block configured to discriminate whether or not the input signal latched by the latch block is defective signal in response to a test mode signal;
- and
- a data output buffer configured to buffer an output signal of the defect discriminating block to transmit it to a data output pin,
- wherein the input signal is one of an input command signal and an input address signal.
A semiconductor memory apparatus, comprising:
- a first defect discriminating block configured to discriminate whether or not a command signal transmitted from a first input pin and latched is defective to generate a first defect discriminating signal in response to a test mode signal;
- a first data output buffer configured to buffer the first defect discriminating signal to transmit the buffered first defect discriminating signal to a first data output pin;
- a decoding block configured to generate a decoded command signal and a decoded address signal by decoding the latched command signal and an address signal transmitted from a second input pin and latched, to control output of the decoded command signal and the decoded address signal to a core circuit area in response to the test mode signal;
- a second defect discriminating block configured to discriminate whether or not the decoded address signal is defective to generate a second defect discriminating block signal;
- and
- a second data output buffer configured to buffer the second defect discriminating signal to transmit the buffered second defect discriminating signal to a second data output pin.
A semiconductor memory apparatus, comprising:
- a command decoding block configured to generate a decoded command signal and a command strobe signal by using a command signal transmitted from a first input pin and latched in response to a test mode signal;
- an address decoding block configured to generate a decoded address signal by using an address signal transmitted from a second input pin and latched in response to the command strobe signal;
- a defect discriminating block configured to discriminate whether or not the decoded address signal is defective to generate a defect discriminating signal in response to the test mode signal;
- and
- a data output buffer configured to buffer the defect discriminating signal to transmit the buffered defect discriminating signal to a data output pin.
Dependencies are inferred from the claim text.