US 2009/0257262 A1 · DRAM AND MEMORY ARRAY

Abstract

A dynamic random access memory (DRAM) includes a substrate, a plurality of bit lines, a plurality of word lines, a plurality of recess channels, a plurality of conductive plugs and a plurality of trench capacitors. In the DRAM, the bit lines are disposed on the substrate in a first direction, and the word lines are disposed on the bit lines in a second direction. Each recess channel is in the substrate between two bit lines below the word line, and each conductive plug connects each recess channel and the word lines. Each trench capacitor is disposed in the substrate between two bit lines where the recess channels are not formed. Because the word lines can be electrically connected with the recess channels directly without using an additional chip area, the WL access time can be accelerated without an increase of the chip size.

Claims25

Dependent claims

A dynamic random access memory (DRAM), comprising:

a substrate;
a plurality of bit lines, disposed on the substrate in a first direction;
a plurality of word lines, disposed on the bit lines in a second direction;
a plurality of recess channels, disposed in the substrate between two adjacent bit lines below the word lines;
a plurality of conductive plugs, connecting each of the word lines and the recess channels;
and
a plurality of trench capacitors, disposed in the substrate between the two adjacent bit lines except where the recess channels are disposed.

4 more elements

Dependencies are inferred from the claim text.

Dram and memory array

Life of this patent

Dram and memory array

Life of this patent

Abstract

Claims25