Low power flip flop through partially gated slave clock
AssigneeAdvanced Micro Devices, Inc.
InventorSamuel D. Naffziger
Life of this patent
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Abstract
A system and method for reducing power consumption within a flip-flop circuit on a semiconductor chip. A gated input clock signal is received by a slave latch. The gated input clock is derived from an ungated input clock signal and a clock gating condition. The clock gating condition determines when an input data signal of the flip-flop and the stored internal state of the slave latch have the same logic value, such as only a logic low value. If they have the same value, toggling of the ungated input clock signal is not received by the slave latch, signal switching of internal nodes of the slave latch is reduced, and power consumption is reduced.
Claims20
A flip-flop circuit comprising:
- a first stage configured to:
- receive an input data signal;
- and
- receive an ungated first input clock signal;
- and
- a second stage configured to:
- receive a gated second input clock signal;
- and
- store a prebuffered data output;
- wherein the gated second input clock signal is:
- dependent upon an ungated second input clock signal, in response to detecting both the input data signal and the prebuffered data output have a same logic value;
- and
- not dependent on the ungated second input clock signal, in response to detecting the input data signal and the prebuffered data output do not have the same logic value.
A clock gating method in a flip-flop circuit, the method comprising:
- receiving in a first stage an input data signal and an ungated first input clock signal;
- receiving in a second stage a gated second input clock signal and storing in the second stage a prebuffered data output;
- wherein the gated second input clock signal is:
- dependent upon an ungated second input clock signal, in response to detecting both the input data signal and the prebuffered data output have a same logic value;
- and
- not dependent on the ungated second input clock signal, in response to detecting the input data signal and the prebuffered data output do not have the same logic value.
Dependencies are inferred from the claim text.