Apparatus and method for a chip assembly including a frequency extending device

The chip assembly according to claim 12, wherein the frequency extending device has a second conductive layer,

• wherein the conductive traces of the frequency extending device have a first plurality of conductive traces, one or more vias, and a second plurality of conductive traces,
• wherein the first plurality of conductive traces are on the first conductive layer, and the second plurality of conductive traces are on the second conductive layer,
• wherein the plurality of bond wires connect the conductive contacts of the chips to the first plurality of conductive traces of the frequency extending device, and
• wherein the second plurality of conductive traces of the frequency extending device are connected to the plurality of conductive lands without using bond wires.

A chip assembly, comprising:

• a chip having a front surface, a rear surface and a side, the chip having conductive contacts;
• a substrate coupled to the chip, the substrate having a front surface, a rear surface and a side;
• an interface layer disposed between the rear surface of the chip and the front surface of the substrate;
• a frequency extending device having at least a first conductive layer and a first dielectric layer, the first conductive layer having one or more conductive traces, the frequency extending device disposed at least partially adjacent to the side of the chip and disposed at least partially overlying the substrate;
• and
• a plurality of conductive lands, at least one of the conductive contacts of the chip connected to one of the one or more conductive traces of the frequency extending device, the at least one of the one or more conductive traces of the frequency extending device connected to one of the plurality of conductive lands, the frequency extending device configured to reduce impedance discontinuity such that the impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by one or more bond wires if such one or more bond wires were to be used in place of the frequency extending device.

A method of manufacturing chip assemblies, comprising:

• providing a plurality of metal lead frames formed in a fixed-attached array, each of the plurality of metal lead frames having a paddle in a center region and a plurality of conductive lands in a peripheral region, the plurality of conductive lands surrounding the paddle, the plurality of conductive lands discretely defined and arranged inwardly toward the paddle;
• attaching a plurality of chips to the plurality of metal lead frames, the step of attaching a plurality of chips comprising:
• attaching each of the plurality of chips to a corresponding one of the paddles, each of the plurality of chips having a front surface, a rear surface and a side, each of the plurality of chips overlying the corresponding one of the paddles, each of the plurality of chips having conductive contacts on its front surface;
• attaching a plurality of frequency extending devices to the plurality of metal lead frames, the step of attaching a plurality of frequency extending devices comprising:
• disposing each of the plurality of frequency extending devices at least partially adjacent to the side of a corresponding one of the plurality of chips and at least partially overlying a corresponding one of the paddles, each of the plurality of frequency extending devices having at least a first conductive layer and a first dielectric layer, the first conductive layer having one or more conductive traces, each of the plurality of frequency extending devices configured to provide a lower discontinuity in impedance as compared to one or more bond wires;
• connecting at least one of the conductive contacts of each of the plurality of chips to at least one of the one or more conductive traces of a corresponding one of the plurality of frequency extending devices;
• and
• connecting at least one of the one or more conductive traces of each of the plurality of frequency extending devices to at least one of the plurality of conductive lands of a corresponding one of the plurality of metal lead frames;
• encapsulating the chip assemblies, each of the chip assemblies having a corresponding one of the plurality of metal lead frames, a corresponding one of the plurality of chips, and a corresponding one of the plurality of frequency extending devices;
• and
• separating the chip assemblies from the fixed-attached array into individual packages.