US 2009/0256183 A1Published application

Single Gate Nonvolatile Memory Cell With Transistor and Capacitor

AssigneeMacronix International Co., Ltd.

InventorsCheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu

Life of this patent

Estimating the term…

Loading patent…

Abstract

A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices.

Claims21

Dependent claims

A nonvolatile memory integrated circuit, comprising:

a semiconductor substrate;
a nonvolatile memory device on the semiconductor substrate, including:
a transistor on the semiconductor substrate controlled by a gate region and by a source region and a drain region having a first doping type, comprising:
first doping regions having the first doping type, the first doping regions positioned on both sides of the gate region, the first doping regions overlapping the source region and the drain region;
second doping regions having a second doping type opposite to the first doping type, the second doping regions positioned on both sides of the gate region, the second doping regions overlapping the source region and the drain region;
third doping regions having the first doping type, the third doping regions positioned on both sides of the gate region, the third doping regions overlapping the source region and the drain region;
fourth doping regions having the first doping type, the fourth doping regions positioned on both sides of the gate region, the fourth doping regions defining the source region and the drain region;
a capacitor on the semiconductor substrate controlled by a gate region;
a shared floating gate connected to the gate region of the transistor and the gate region of the capacitor.

6 more elements

A nonvolatile memory integrated circuit, comprising:

a semiconductor substrate;
a plurality of nonvolatile memory devices on the semiconductor substrate, each including:
a transistor on the semiconductor substrate controlled by a gate region and by a source region and a drain region having a first doping type, comprising:
first doping regions having the first doping type, the first doping regions positioned on both sides of the gate region, the first doping regions overlapping the source region and the drain region;
second doping regions having a second doping type opposite to the first doping type, the second doping regions positioned on both sides of the gate region, the second doping regions overlapping the source region and the drain region;
third doping regions having the first doping type, the third doping regions positioned on both sides of the gate region, the third doping regions overlapping the source region and the drain region;
fourth doping regions having the first doping type, the fourth doping regions positioned on both sides of the gate region, the fourth doping regions defining the source region and the drain region;
a capacitor on the semiconductor substrate controlled by a gate region;
a shared floating gate connected to the gate region of the transistor and the gate region of the capacitor.

6 more elements

A method of manufacturing a nonvolatile memory integrated circuit, comprising:

providing a semiconductor substrate;
providing a nonvolatile memory device on the semiconductor substrate, including:
providing 1) a transistor on the semiconductor substrate controlled by a first gate region and by a source region and a drain region having a first doping type, and 2) a capacitor on the semiconductor substrate controlled by a second gate region, comprising:
providing first doping regions having the first doping type, the first doping regions positioned on both sides of the first gate region, the first doping regions overlapping the source region and the drain region;
providing second doping regions having a second doping type opposite to the first doping type, the second doping regions positioned on both sides of the first gate region, the second doping regions overlapping the source region and the drain region;
providing third doping regions having the first doping type, the third doping regions positioned on both sides of the first gate region, the third doping regions overlapping the source region and the drain region;
providing fourth doping regions having the first doping type, the fourth doping regions positioned on both sides of the first gate region and on both sides of the second gate region, the fourth doping regions defining the source region and the drain region;
providing a shared floating gate connected to the first gate region of the transistor and the second gate region of the capacitor.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/102,608Filed 14 Apr 2008
Published: 15 Oct 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/0411
Of FETs having insulated gates [IGFET]: of FETs having floating gates
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
H10D 30/68
Insulated-gate field-effect transistors [IGFET]: floating-gate IGFETs