Semiconductor memory device and method of manufacturing the same
AssigneeElpida Memory, Inc.
InventorMitsunari SUKEKAWA
Life of this patent
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Abstract
A semiconductor memory device includes a memory cell portion and a peripheral circuit portion. The memory cell portion includes a pillar capacitor with a lower electrode, a dielectric film, and an upper electrode sequentially formed on a side surface of a first insulating portion which is parallel to a predetermined direction, and a transistor electrically connected to the lower electrode. The peripheral circuit portion includes a plate electrode, a cylinder capacitor with an upper electrode, a dielectric film, and a lower electrode sequentially formed on a side surface of the plate electrode which is parallel to the predetermined direction, and a transistor electrically connected to the lower electrode.
Claims17
A semiconductor memory device including a memory cell portion and a peripheral circuit portion,
- wherein the memory cell portion comprises:
- a first insulating portion extending in a predetermined direction;
- a capacitor including a lower electrode, a dielectric film, and an upper electrode sequentially formed on a side surface of the first insulating portion which is parallel to the predetermined direction;
- a plate electrode electrically connected to the upper electrode;
- and
- a transistor including a source region and a drain region one of which is electrically connected to the lower electrode, and
- the peripheral circuit portion comprises:
- a plate electrode extending in the same direction as the predetermined direction;
- a capacitor including an upper electrode, a dielectric film, and a lower electrode sequentially formed on a side surface of the plate electrode which is parallel to the predetermined direction;
- and
- a transistor including a source region and a drain region one of which is electrically connected to the lower electrode.
A method of manufacturing a semiconductor memory device, the method comprising:
- forming a transistor and a contact plug in a memory cell portion forming region and a peripheral circuit portion forming region, the contact plug being electrically connected to one of a source region and a drain region of the transistor;
- depositing an interlayer insulating film all over the memory cell portion forming region and the peripheral circuit portion forming region;
- forming a plurality of first openings in the interlayer insulating film in the memory cell portion forming region such that the contact plug is exposed, and forming a second opening in the interlayer insulating film in the peripheral circuit portion forming region so as to enclose a predetermined region and to expose the contact plug;
- depositing a conductive material on an inner wall of each of the first and second openings so as to leave an opening portion unfilled, to form a lower electrode;
- filling an insulating material in each of the first openings with the lower electrode formed therein, to form a first insulating portion, and filling an insulating material into the second opening with the lower electrode formed therein;
- removing the interlayer insulating film from the memory cell portion forming region and removing the interlayer insulating film composing the predetermined region in the peripheral circuit portion forming region to form a third opening;
- depositing a dielectric film so as to cover a surface of the lower electrode in the memory cell portion forming region with the dielectric film and to cover an inner wall of the third opening in the peripheral circuit portion forming region with the dielectric film;
- filling a conductive material, in the memory cell portion forming region, between the first insulating portions each formed with the dielectric film and the lower electrode, to form an upper electrode, and depositing a conductive material in the third opening so as to leave an opening portion unfilled in the peripheral circuit portion forming region to form an upper electrode;
- and
- forming a plate electrode in the memory cell portion forming region such that the plate electrode is electrically connected to the upper electrode, and filling a conductive material into the opening portion of the third opening in the peripheral circuit portion forming region to form a plate electrode.
A semiconductor memory device comprising:
- a memory cell portion including a plurality of first capacitors, each of the first capacitors including a first lower electrode formed along a first insulating wall, a first upper electrode, and a first dielectric film formed between the first lower electrode and the first upper electrode;
- and
- a peripheral circuit portion including at least one second capacitor, the second capacitor including a second lower electrode formed along a second insulating wall, a second upper electrode, and a second dielectric film formed between the second lower electrode and the second upper electrode.
Dependencies are inferred from the claim text.