US 2009/0256173 A1 · COMPLEMENTARY FIELD EFFECT TRANSISTORS HAVING EMBEDDED SILICON SOURCE AND DRAIN REGIONS

Abstract

A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions. The difference between the lattice constant of silicon and that of the underlying first and second regions results in tensile stressed silicon over the first semiconductor region and compressive stressed silicon over the second semiconductor region.

Claims20

Dependent claims

A method of fabricating semiconductor devices, comprising:

(a) epitaxially growing a first semiconductor region on an underlying semiconductor region of a substrate, such that the first semiconductor region grows laterally adjacent to a second semiconductor region of the substrate, the first semiconductor region having a lattice constant larger than that of silicon and the second semiconductor region having a lattice constant smaller than that of silicon;
(b) growing layers each consisting essentially of silicon onto exposed major surfaces of the first and second semiconductor regions;
(c) forming gates overlying the epitaxially grown silicon layers;
(d) removing portions of the first and second semiconductor regions adjacent to the gates to form recesses;
and
(e) epitaxially growing regions consisting essentially of silicon within the recesses;
and
(f) forming source and drain regions extending at least partially in the silicon regions epitaxially grown in step (e), wherein the epitaxially grown silicon layer overlying the first semiconductor region forms a tensile stressed channel region of an n-type field effect transistor (“NFET”) and the epitaxially grown silicon layer overlying the second semiconductor region forms a compressive stressed channel region of a p-type field effect transistor (“PFET”).

5 more elements

Dependencies are inferred from the claim text.

Complementary field effect transistors having embedded silicon source and drain regions

Life of this patent

Complementary field effect transistors having embedded silicon source and drain regions

Life of this patent

Abstract

Claims20