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US 2009/0256133 A1Published application
Multiple layer resistive memory
OwnerDerchang Kau, Richard E. Fackenthal +1inventors
InventorsDerchang Kau, Richard E. Fackenthal, Ferdinando Bedeschi
Life of this patent
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Abstract
A resistive memory cell may be composed of four stacked layers. Each layer may be sandwiched by electrodes. Connections may be formed from each of four directions around the stack, for example, aligned with each of four edges where the resistive layers are rectangular.
Claims30
A method comprising:
- forming a vertical stack of at least four resistive memory layers;
- and
- providing at least four connections to said vertical stack for accessing the layers of said stack.
A resistive memory comprising:
- a vertical stack including at least four resistive memory layers;
- and
- at least four electrical connections to said vertical stack to enable each of said layers to be accessed.
A resistive memory comprising:
- at least four vertically spaced resistive memory material layers;
- a plurality of conductors, sandwiching one or more of said layers;
- and
- one of said conductors extending in each of four different directions.
1 more element
A system comprising:
- a processor;
- and
- a resistive memory coupled to said processor, said memory including a cell with at least four stacked resistive memory layers and a plurality of electrodes arranged in two transverse directions, sandwiching each layer.
Dependencies are inferred from the claim text.