# US 2009/0255705 A1 · Method of Creating Alignment/Centering Guides for Small Diameter, High Density Through-Wafer Via Die Stacking

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- Number: US 2009/0255705 A1
- Document ID: US20090255705A1
- Status: Published application
- Kind: A1
- Application number: 12/101,776
- Filed: 2008-04-11
- Published: 2009-10-15
- Earliest claimed: 2008-04-11
- Assignees: Micron Technology, Inc.
- Inventors: Dave Pratt
- Web page: https://patentgrep.com/patent/US20090255705A1

## CPC

- H10W 90/00: Package configurations
- H10D 62/117: {Shapes of semiconductor bodies}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/07227: {involving guiding structures, e.g. spacers or supporting members}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/251: {Materials}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/285: {Alignment aids, e.g. alignment marks}
- H10W 80/168: {using guiding structures}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- Y10T 29/49117: Conductor or circuit manufacturing
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A method if provided for forming a die stack. The method includes forming a plurality of through-wafer vias and a first plurality of alignment features in a first die. A second plurality of alignment features is formed in a second die, and the first die is stacked on the second die such that the first plurality of alignment features engage the second plurality of alignment features. A method of manufacturing a die stack is also provided that includes forming a plurality of through-wafer vias on a first die, forming a plurality of recesses on a first die, and forming a plurality of protrusions on a second die. A die stack and a system are also provided.

## Claims

### Claim 1

A method of forming a die stack, comprising:
forming a plurality of through-wafer vias in a first die; and
forming one or more alignment features in a first die.

### Claim 2 (depends on 1)

The method of claim 1, comprising creating one or more alignment features in a second die.

### Claim 3 (depends on 1)

The method of claim 1, comprising stacking the second die on the first die.

### Claim 4 (depends on 1)

The method of claim 1, wherein the alignment features comprise a plurality of openings.

### Claim 5 (depends on 1)

The method of claim 1, wherein the plurality of openings extend at least as far from the surface of the die as the plurality of through-wafer vias.

### Claim 6 (depends on 1)

The method of claim 1, wherein the alignment features comprise a plurality of protrusions extending from the die.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the one or more alignment features comprises forming the alignment features by photolithography, stereolithography, wet etch, dry etch, passivation, or a combination thereof.

### Claim 8 (depends on 1)

The method of claim 1, comprising picking the first die and placing the first die onto the second die such that the alignment features of the first die engage the alignment features of the second die.

### Claim 9 (depends on 1)

The method of claim 1, comprising placing the die stack in a curing oven.

### Claim 10

A method of manufacturing a die stack, comprising:
forming a plurality of through-wafer vias on a first die;
forming a plurality of recesses on a first die; and
forming a plurality of protrusions on a second die, wherein the plurality of protrusions are configured to engage the plurality of recesses to align a plurality of bond pads of the second die with the plurality of through-wafer vias of the first die.

### Claim 11 (depends on 9)

The method of claim 9, comprising stacking the first die onto the second die such that the plurality of recesses engage the plurality of protrusions.

### Claim 12 (depends on 9)

The method of claim 9, comprising stacking the second die onto the first die such that the plurality of protrusions engage the plurality of recesses.

### Claim 13 (depends on 9)

The method of claim 9, wherein forming the plurality of recesses on a first die comprises forming a plurality of recesses in a layer disposed on the first day.

### Claim 14 (depends on 12)

The method of claim 12, wherein the layer comprises a passivation layer.

### Claim 15

A method of manufacturing a semiconductor device, comprising:
forming a plurality of alignment features in a wafer;
dicing the wafer into a plurality of dies, such that each die comprises one or more of the plurality of alignment features;
forming a plurality of through-wafer vias in a first die of the plurality of dies.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming a plurality of alignment features comprising forming the plurality of alignment features at a plurality of die streets of the wafer.

### Claim 17

A die stack, comprising:
a first die having a first plurality of alignment features and a plurality of through-wafer vias; and
a second die having a second plurality of alignment features and a plurality of bond pads, wherein the second plurality of alignment features of the second die are configured to engage the first plurality of alignment features of the first die, such that the plurality of bond pads of the second die align with the plurality of through-wafer vias of the first die.

### Claim 18 (depends on 9)

The die stack of claim 9, wherein the plurality of bond pads of the second die are configured to engage the plurality of through-wafer vias of the first die.

### Claim 19 (depends on 15)

The die stack of claim 15, wherein the first plurality of alignment features comprises a plurality of recesses.

### Claim 20 (depends on 17)

The die stack of claim 17 wherein the second plurality of alignment features comprises a plurality of protrusions extending from the surface of the die.

### Claim 21 (depends on 15)

The die stack of claim 15, wherein the first plurality of alignment features and the second plurality of alignment features comprise a plurality of protrusions.

### Claim 22

A system comprising:
an electronic device comprising:
a processor;
one or more semiconductor devices, wherein the one more semiconductor devices comprises a die stack, wherein the die stack comprises a first die having a first plurality of alignment features and through-wafer vias.

### Claim 23 (depends on 21)

The system of claim 21, wherein the die stack of claim 21, wherein the die stack comprises a second die having a second plurality of alignment features.

### Claim 24

A die stack, comprising:
a first die having a first plurality of protrusions and a plurality of through-wafer vias; and
a second die having a second plurality of protrusions, wherein the second plurality of protrusions are configured to engage the first plurality of protrusions.