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US 2009/0254705 A1Published application
Bus attached compressed random access memory
AssigneeInternational Business Machines Corporation
InventorsBulent Abali, John P. Karidis, Luis A. Lastras-Montano
Life of this patent
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Abstract
A computer memory system having a three-level memory hierarchy structure is disclosed. The system includes a memory controller, a volatile memory, and a non-volatile memory. The volatile memory is divided into an uncompressed data region and a compressed data region.
Claims11
A computer memory system having a multi-level hierarchical memory structure, the computer memory system comprising:
- a first-type memory being a volatile memory and having a uncompressed data region (L3) and a compressed data region (L4);
- a second-type memory (L5) being an non-volatile memory, being slower than the first-type memory, having more capacity than the first-type memory, and storing compressed data;
- and
- a memory controller means for controlling a direct I/O access to the first-type memory and the second-type memory, for controlling data exchange between the first-type memory and the second-type memory (L5) in response to an issuance of a memory access request from a general purpose processor, and for controlling data exchange between the uncompressed data region (L3) and the compressed data region (L4) in the first-type memory according to an issuance of a memory accesses request from the general purpose processor.
1 more element
Dependencies are inferred from the claim text.