Multi port memory device with shared memory area using latch type memory cells and driving method

A multiprocessor system comprising:

• a first processor performing a first task;
• a second processor performing a second task;
• and
• a multiport semiconductor memory device comprising:
• first and second port units respectively coupled to the first and second processors;
• a first dedicated memory area accessed by only the first processor via the first port unit and implemented using Dynamic Random Access Memory (DRAM) cells;
• a second dedicated memory area accessed by only the second processor via the second port unit and implemented using DRAM cells;
• a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas;
• and
• a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area;

A method of driving a multiport semiconductor memory device in a multiprocessor system including the multiport semiconductor memory device operationally coupled with first and second processors individually performing first and second tasks, the method comprising:

• preparing in the multiport semiconductor memory device, first and second port units individually coupled corresponding to the first and second processors, dedicated memory areas accessed dedicatedly by the processors corresponding to the port units and comprised of DRAM cells, and a shared memory area accessed in common by the processors through the port units, comprised of memory cells of a type different from the dedicated memory areas and assigned in a predetermined memory capacity unit at a portion of memory cell array;
• forming a data access path between the shared memory area and one port selected from the port units in response to external signals applied from the processors;
• and
• using an internal register accessed substitutionally corresponding to a specific address of the shared memory area to provide a DRAM interface function in a communication between the processors.