Memory with embedded associative section for computations
AssigneeZikbit Ltd.
InventorsAvidan Akerib, Eli Ehrman, Yoav Lavi, Moshe Meyassed
Life of this patent
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Abstract
An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data.
Claims41
An integrated circuit device comprising:
- a semiconductor substrate;
- an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data;
- and
- a computational section comprising associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data.
A method for computing, comprising:
- accepting and executing at least one command from a host processor to a memory device, the at least one command comprising a write command to store data at a specified address in an array of random access memory (RAM) cells formed on a semiconductor substrate in the memory device;
- responsively to the at least one command, transferring the data into a computational section of the memory device, the computational section comprising associative memory cells, which are disposed on the semiconductor substrate in communication with the array of the RAM cells;
- and
- performing an associative computation on the data in the computational section.
An integrated circuit device, comprising:
- a semiconductor substrate;
- an array of random access memory (RAM) cells, which are disposed on the substrate and are configured to store data;
- a computational section comprising associative memory cells, which are disposed on the substrate in communication with the array of the RAM cells;
- and
- control logic, which is configured to accept and execute first commands from a host processor specifying read and write operations to be performed on the data in the RAM cells, and to accept second commands from the host processor, which cause the computational section to perform associative computations on the data.
A method for computing, comprising:
- providing a memory device comprising an array of random access memory (RAM) cells, which are disposed on a semiconductor substrate and are configured to store data, and comprising a computational section, which comprises associative memory cells, which are disposed on the substrate in communication with the array of the RAM cells;
- in response to first commands from a host processor to the memory device, performing read and write operations on the data in the RAM cells;
- and
- in response to second commands from the host processor to the memory device, performing associative computations on the data in the computational section.
Dependencies are inferred from the claim text.