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US 2009/0253256 A1Published application
Methods of fabricating semiconductor devices having transistors with different gate structures
AssigneeSamsung Electronics Co., Ltd.
InventorsHye-Lan Lee, Yu-Gyun Shin, Sang-Bom Kang, Hag-Ju Cho, Seong-Geon Park, Taek-Soo Jeon
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Abstract
A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.
Claims5
A method of fabricating a semiconductor device, comprising:
- forming a gate insulation film on a substrate including memory cell and peripheral circuit regions;
- selectively forming a first metal layer on the gate insulation film of a second-conductivity transistor region of the peripheral circuit region;
- forming a doped silicon layer on the gate insulation film in a first-conductivity transistor region of the peripheral circuit region and on the gate insulation film in the memory cell region, and on the first metal layer;
- and
- patterning the first metal layer and the doped silicon layer to form a first gate structure comprising the doped silicon layer in the memory cell region and the first-conductivity transistor region of the peripheral circuit region and to form a second gate structure comprising the first metal layer and the doped silicon layer in the second-conductivity transistor region of the peripheral circuit region.
2 more elements
A method of fabricating a semiconductor device, comprising:
- forming a gate insulation film on a substrate including memory cell and peripheral circuit regions;
- forming a first doped silicon layer on the gate insulation film in the memory cell region and a first-conductivity transistor region of the peripheral circuit region;
- forming a first metal layer on the gate insulation film of a second-conductivity transistor region of the peripheral circuit region;
- forming a second doped silicon layer on the first doped silicon layer and the first metal layer;
- and
- patterning the first metal layer, and the first and second doped silicon layers to form a first gate structure comprising the first and second doped silicon layers in the memory cell region and first-conductivity transistor region of the peripheral circuit region and to form a second gate structure comprising the first metal layer and the second doped silicon layer in the second-conductivity transistor region of the peripheral circuit region.
3 more elements
Dependencies are inferred from the claim text.