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US 2009/0253239 A1Published application
Method and structure for ballast resistor
AssigneeInternational Business Machines Corporation
InventorsDouglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Robert M. Rassel, Kimball M. Watson
Life of this patent
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Abstract
A method for fabricating a low-value resistor such as a ballast resistor for bipolar junction transistors. The resistor may be fabricated using layers of appropriate sheet resistance so as to achieve low resistance values in a compact layout. The method may rely on layers already provided by a conventional CMOS process flow, such as contact plugs and fully silicided (FUSI) metal gates.
Claims2
(canceled)
A semiconductor device comprising:
- a dielectric layer formed by a shallow trench isolation process;
- a bipolar transistor having collector, base and emitter regions, the collector region being in lateral contact with the dielectric layer;
- a contact bar formed by a contact plug process over the dielectric layer, the contact bar having a longitudinal dimension and a transverse dimension, the transverse dimension being smaller than a maximum dimension allowed by a design rule of the contact plug process, a first end of the contact bar in a longitudinal direction being in electrical contact with the emitter region, the contact bar being isolated from the base region by a dielectric sidewall spacer;
- and
- a metal pad disposed over and in contact with a second end of the contact bar in the longitudinal direction;
- whereby the resistance of the ballast resistor is substantially determined by the ratio of the longitudinal dimension to the transverse dimension.
3 more elements
Dependencies are inferred from the claim text.