Data Driver Circuit for a Dynamic Random Access Memory (DRAM) Controller or the Like and Method Therefor

A data driver comprising:

• a first latch having an input for receiving an input data signal, a clock input for receiving a first clock signal, and an output;
• an extension logic circuit having an input coupled to said output of said first latch, a control input for receiving a control signal, and an output, wherein said extension logic circuit selectively delays said output of said first latch in response to said control signal;
• and
• a second latch having an input coupled to said output of said extension logic circuit, a clock input for receiving a second clock signal, and an output for providing an output data signal.

A method comprising:

• latching data in response to a first clock signal to provide latched data;
• selectively delaying said latched data in response to a control signal to provide selectively delayed data;
• and
• re-latching said selectively delayed data in response to a second clock signal.