US 2009/0244995 A1 · Circuit for Locking a Delay Locked Loop (DLL) and Method Therefor

Abstract

A receive circuit (320) includes a DLL core (510), a latch (326), and a DLL control circuit (520). The DLL core (510) has a first input for receiving a DLL clock signal, a second input for receiving a delay line select signal, and an output for providing a delayed data strobe signal. The latch (326) has a signal input for receiving an external data signal, a control input coupled to the output of the DLL core (510), and an output for providing an internal data signal. The DLL control circuit (520) provides the DLL clock signal to the first input of the DLL core (510) responsive to a memory data strobe signal while the receive circuit is in a first mode, and provides the DLL clock signal to the first input of the DLL core (510) responsive to a processor clock signal while the receive circuit (320) is in a second mode.

Claims20

Dependent claims

A dynamic random access memory (DRAM) controller comprising:

a delay locked loop (DLL) core having a first input for receiving a DLL clock signal, a second input for receiving a delay line select signal, and enable input, and an output for providing a delayed memory data strobe signal;
and
a DLL control circuit coupled to said DLL core for providing said DLL clock signal to said first input of said DLL core responsive to a memory data strobe signal during read cycles, for providing said DLL clock signal to said first input of said DLL core responsive to a processor clock signal during cycles other than said read cycles, and for enabling said DLL core to lock during at least a portion of said read cycles.

Dependencies are inferred from the claim text.

Circuit for Locking a Delay Locked Loop (DLL) and Method Therefor

Life of this patent

Circuit for Locking a Delay Locked Loop (DLL) and Method Therefor

Life of this patent

Abstract

Claims20