Maintaining dynamic count of fifo contents in multiple clock domains
AssigneeLSI Corporation
InventorsJohn Udell, Richard Solomon, Eugene Saghi, Jeffrey K. Whitt
Life of this patent
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AssigneeLSI Corporation
InventorsJohn Udell, Richard Solomon, Eugene Saghi, Jeffrey K. Whitt
Estimating the term…
Disclosed is a system that generates a write count value for indicating whether data can be read from a FIFO and a system that generates a read count value for indicating whether data can be written to a FIFO. Each of these systems operates in two separate clock domains. In the system that generates a write count value, write strobes are stored in parallel in a register in a first clock domain. The plurality of synchronizers trigger on a rising edge of the write strobe that is stored in the parallel register and generate an increment pulse in a second clock domain. An up/down counter reads the increment pulse in parallel and increments the up/down counter in parallel. A decrement signal from a read strobe decrements the up/down counter. The output of the counter is fed to a register that provides a write counter value to handshake logic that indicates whether data can be read from a FIFO without underflowing the FIFO.
A method of generating a write count value in a read clock domain from write strobes generated in a write clock domain indicating an amount of data that is present in a FIFO comprising:
A method of generating a read count value in a write clock domain from read strobes generated in a read clock domain indicating a number of open slots present in a FIFO comprising:
A device for generating a write counter value in a read clock domain to indicate the amount of data that is present in a FIFO comprising:
A device for generating a read counter value in a write clock domain from read strobes generated in a read clock domain to indicate the number of slots open in a FIFO comprising:
Dependencies are inferred from the claim text.