Random Access Decoder

A readout circuit comprising at least one decoder, each decoder comprising a plurality of decoder circuit elements and means for applying an input signal to each of the decoder circuit elements, wherein each decoder circuit element has a unique electronic address and a binary data output and places data on its binary data output only when the unique electronic address of a particular decoder circuit element matches the applied input signal, the unique electronic address of each of the plurality of decoder circuit elements being electronically loadable into each of the decoder circuit elements, wherein the readout circuit is adapted for use with an imaging array and further wherein at least two of the decoder circuits element are physically identical.

A readout circuit comprising at least one decoder, each decoder comprising a plurality of decoder circuit elements and means for applying an input signal to each of the decoder circuit elements, wherein each decoder circuit element has a unique electronic address and a binary data output and places data on its binary data output only when the unique electronic address of a particular decoder circuit element matches the applied input signal, the unique electronic address of each of the plurality of decoder circuit elements being electronically loadable into each of the decoder circuit elements, wherein the readout circuit is adapted for use with an imaging array and further wherein at least two of the decoder circuits element are electrically identical.

A readout circuit formed on an integrated circuit comprising at least one decoder, each decoder comprising a plurality of decoder circuit elements and means for applying an input signal to each of the decoder circuit elements, wherein each decoder circuit element has a unique electronic address and a binary data output and places data on its binary data output only when the unique electronic address of a particular decoder circuit element matches the applied input signal, the unique electronic address of each of the plurality of decoder circuit elements being electronically loadable into each of the decoder circuit elements, wherein at least two of the decoder circuits element are physically identical.

A readout circuit comprising at least one decoder, each decoder comprising a plurality of decoder circuit elements and means for applying an input signal to each of the decoder circuit elements, wherein each decoder circuit element has a unique electronic address and a binary data output and, places data on its binary data output only when the unique electronic address of a particular decoder circuit element matches the applied input signal, the unique electronic address of each of the plurality of decoder circuit elements being electronically loadable into each of the decoder circuit elements, wherein the readout circuit is adapted for use with an imaging array and further comprises a shift register associated with each decoder, each decoder being arranged to load the shift register associated therewith at any point along its length.