# US 2009/0243735 A1 · Frequency diverse discrete-time phase-lock device and apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2009/0243735 A1 - Document ID: US20090243735A1 - Status: Published application - Kind: A1 - Application number: 12/058,243 - Filed: 2008-03-28 - Published: 2009-10-01 - Earliest claimed: 2008-03-28 - Assignees: Agilent Technologies, Inc. - Inventors: David A. Luiz; Robert J. Buck - Web page: https://patentgrep.com/patent/US20090243735A1 ## CPC - H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence) - H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A discrete-time phase lock loop (DTPLL) includes an analog section comprising a digital-to-analog converter (DAC) and an oscillator, operative to provide a clock signal based on an input from the DAC. The DTPLL also includes a digital signal processor (DSP). The DSP includes a loop controller state machine; a phase detector; a counter, operative to receive clock signals from the oscillator and to provide a count value to the phase detector; a divider, operative to receive a reference signal and to provide a reference pulse output to the phase detector; and a loop filter operative to provide a control effort value based on an output from the phase detector. Based on the phase error value, an output of the oscillator is changed to reduce the phase error to a steady state value. ## Claims ### Claim 1 A discrete-time phase lock loop (DTPLL), comprising: an analog section comprising a digital-to-analog converter (DAC) and an oscillator, operative to provide a clock signal based on an input from the DAC; and a digital signal processor (DSP) comprising: a loop controller state machine; a phase detector; a counter, operative to receive clock signals from the oscillator and to provide a count value to the phase detector; a divider, operative to receive a reference signal and to provide a reference pulse output to the phase detector; and a loop filter operative to provide a control effort value based on an output from the phase detector, wherein, based on the phase error value an output of the oscillator is changed to reduce the phase error to a steady state value. ### Claim 2 (depends on 1) A DTPLL as claimed in claim 1, wherein the DSP comprises a field programmable gate array (FPGA). ### Claim 3 (depends on 2) A DTPLL as claimed in claim 2, wherein the counter, the divider and the loop filter each comprise respective registers having operational parameters. ### Claim 4 (depends on 1) A DTPLL as claimed in claim 1, wherein the DSP further comprises a phase lock detector, operative to compare the phase error with a threshold and to provide an output to the loop controller state machine indicative of the lock state of the DTPLL. ### Claim 5 (depends on 1) A DTPLL as claimed in claim 1, wherein the loop filter comprises a proportional integral (PI) filter. ### Claim 6 (depends on 1) A DTPLL as claimed in claim 1, wherein the loop filter comprises a proportional integral derivative (PID) filter. ### Claim 7 (depends on 6) A DTPLL as claimed in claim 6, wherein the PID filter provides a signal to the DAC, which drives the oscillator based on the control effort. ### Claim 8 (depends on 7) A DTPLL as claimed in claim 7, wherein the signal from the PID filter further comprises a control effort further comprises a finite bit word, which is added to a calibration value at an adder, and the output from the adder is representative of a change required in an output of the oscillator. ### Claim 9 (depends on 1) A DTPLL as claimed in claim 1, wherein the counter has a maximum value, N, and the divider divides by a reference value, M, and a phase lock condition is approximately: (fo/N)=(fref/M), where fo is an oscillator frequency and fref is a reference clock frequency. ### Claim 10 (depends on 1) A DTPLL as claimed in claim 1, wherein the oscillator is a voltage controlled oscillator (VCO). ### Claim 11 An instrument, comprising: a discrete-time phase lock loop (DTPLL), comprising: an analog section comprising a digital-to-analog converter (DAC) and an oscillator, operative to provide a clock signal based on an input from the DAC; and a digital signal processor (DSP) comprising: a loop controller state machine; a phase detector; a counter, operative to receive clock signals from the oscillator and to provide a count value to the phase detector; a divider, operative to receive a reference signal and to provide a reference pulse output to the phase detector; and a loop filter operative to provide a control effort value based on an output from the phase detector, wherein, based on the phase error value an output of the oscillator is changed to reduce the phase error to a steady state value. ### Claim 12 (depends on 11) An instrument as claimed in claim 11, wherein the DSP comprises a field programmable gate array (FPGA). ### Claim 13 (depends on 12) An instrument as claimed in claim 12, wherein the counter, the divider and the loop filter each comprise respective registers having operational parameters. ### Claim 14 (depends on 11) An instrument as claimed in claim 11, wherein the DSP further comprises a phase lock detector, operative to compare the phase error with a threshold and to provide an output to the loop controller state machine indicative of the lock state of the DTPLL. ### Claim 15 (depends on 11) An instrument as claimed in claim 11, wherein the loop filter comprises a proportional integral (PI) filter. ### Claim 16 (depends on 11) An instrument as claimed in claim 11, wherein the loop filter comprises a proportional integral derivative (PID) filter. ### Claim 17 (depends on 16) An instrument as claimed in claim 16, wherein the PID filter provides a signal to the DAC, which drives the oscillator based on the control effort. ### Claim 18 (depends on 17) An instrument as claimed in claim 17, wherein the signal from the PID filter further comprises a control effort further comprising a finite bit word, which is added to a calibration value at an adder, and the output from the adder is representative of a change required in an output of the oscillator. ### Claim 19 (depends on 11) An instrument as claimed in claim 11, wherein the counter has a maximum value, N, and the divider divides by a reference value, M, and a phase lock condition is approximately: (fo/N)=(fref/M), where fo is an oscillator frequency and fref is a reference clock frequency. ### Claim 20 (depends on 11) An instrument as claimed in claim 11, wherein the instrument is a measurement instrument. ### Claim 21 (depends on 20) An instrument as claimed in claim 20, wherein the measurement instrument is a handheld instrument.