SDOC with FPHA & FPXC: System Design On Chip with Field Programmable Hybrid Array of FPAA, FPGA, FPLA, FPMA, FPRA, FPTA and Frequency Programmable Xtaless ClockChip with Trimless/Trimfree Self-Adaptive Bandgap Reference Xtaless ClockChip

Abstract

The Field Programmable Hybrid Array (FPHA) and Frequency Programmable Xtaless Clock (FPXC) are for high-speed and high frequency System-Design-On-Chip(SDOC). The FPXC adopts the Self-Adaptive Process & Temperature Compensation Bandgap Reference Generator, the Gain-Boost Amplitude Control LC VCO and inverter type flash memory. The FPHA adopts the two-way flash switch and inverter type flash memory Look-Up-Table(LUT). The FPXC adopts the inverter type flash memory as the Non-Volatile Memory(NVM) to keep the setup data in the field frequency programming. The flash technology of FPHA and FPXC are compatible that the FPHA has the FPXC capability. The PLLess CDR(PLL free Clock Data Recovery) is based on the FPXC capability for the SerDes high frequency application. The PLLess CDR and pipeline ADC are for the analog front high frequency application. With the SDOC on FPHA, the Automobile Infotainment Center(MIC) is reduced to be Mobile Infotainment Center(MIC). The (1) Capacitorless Low Drop Voltage (Capless LDVR) (2) Inductor less Switch Mode Power Supply (Indless SMPS) (3) Resistorless Current Sensor (Resless CS), (4) Saw Filter Less Low Noise Amplifier(Sawless LNA), (5) Diode Less True Random Number Generator (Dioless TRNG), (6) Crystal Less Clock (Xtaless Clock), (7) PLL Less Clock and Data Recovery (PLLess CDR) and (8) Filmless Touching Screen (FLTS) constitutes the most advanced System Design On Chip (SDOC) on Field Programmable Hybrid Array (FPHA) for Mobile Infotainment Center (MIC).

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