Method and device for generating a digital data signal and use thereof

An integrated circuit, comprising:

• at least one clock signal input;
• at least one control signal input;
• at least one delay unit having an input and an output, wherein said input of said delay unit receives said clock signal and said output delivers a clock signal having an adjustable delay, wherein the delay is controllable by means of said at least one control signal;
• a unit having at least two inputs and at least two outputs, wherein said inputs are adapted to receive at least two clock signals, one of said clock signals being delayed with respect to the other, and wherein said outputs are adapted to provide at least two clock signals, whereby any of said output clock signals do not simultaneously assume the same predetermined logical state;
• at least two data signal inputs;
• at least one data signal output;
• and
• a multiplexor, comprising:
• at least two signal inputs which are coupled to said at least two data signal inputs;
• and
• at least two clock signal inputs which are coupled to the outputs of said unit having at least two inputs and at least two outputs which is adapted to provide at least two clock signals, wherein the multiplexor provides an output signal selected from said at least two data signals, and wherein the at least two data signals are outputted edge-synchronous to the first and second clock signal.

A test device for a semiconductor device comprising an integrated circuit, said integrated circuit comprising:

• at least one clock signal input;
• at least one control signal input;
• at least one delay unit having an input and an output, wherein said input of said delay unit receives said clock signal and said output delivers a clock signal having an adjustable delay, wherein the delay is controllable by means of said at least one control signal;
• a unit having at least two inputs and at least two outputs, wherein said inputs are adapted to receive at least two clock signals, one of said clock signals being delayed with respect to the other, and wherein said outputs are adapted to provide at least two clock signals, whereby any of said output clock signals do not simultaneously assume the same predetermined logical state;
• at least two data signal inputs;
• at least one data signal output, wherein the at least one data signal output is coupled to at least one input of the semiconductor device under test;
• and
• a multiplexor, comprising:
• at least two signal inputs which are coupled to said at least two data signal inputs which are coupled to the outputs of said unit having at least two inputs and at least two outputs which is adapted to provide at least two clock signals, wherein the multiplexor is adapted to provide an output signal selected from said at least two data signals, and wherein the at least two data signals are outputted edge-synchronous to the first and second clock signal.

A method for generating a digital data signal having a variable symbol duration, the method comprising:

• providing at least one first data signal;
• providing at least one first clock signal;
• providing at least one control signal;
• generating at least one second clock signal from the first clock signal, the second clock signal comprising a variable delay and the delay being set depending on the value of the at least one control signal;
• and
• generating a second data signal from the at least one first data signal, wherein said second data signal is edge-synchronous to the first and second clock signal.

A method for testing a semiconductor device, comprising:

• coupling a data signal having a variable symbol length to at least one input of the semiconductor device under test, wherein said data signal having a variable symbol length is generated by means of a method comprising:
• providing at least one first data signal having a constant symbol length;
• providing at least one first clock signal;
• providing at least one control signal;
• generating at least one second clock signal from the first clock signal, the second clock signal comprising a variable delay and the delay being set depending on the value of the at least one control signal;
• and
• generating said data signal having a variable symbol length from the at least one first data signal, wherein said second data signal is edge-synchronous to the first and second clock signals.