Control of localized air gap formation in an interconnect stack

A method for fabricating an interconnect stack (200) of an integrated-circuit device (201), comprising the formation of a plurality of interconnect levels, from a bottom interconnect level (256) at a smallest distance from a reference surface of a substrate to a top interconnect level (283) at a largest distance from the reference surface, the method comprising the steps of:

• fabricating respective interconnect levels, which contain metal interconnect line sections (230, 204) extending parallel to the reference substrate surface and between intermetal-dielectric layer sections (220) of the respective interconnect level,
• fabricating a lower etch-barrier layer (236), which is impermeable for a selective etchant that attacks the intermetal-dielectric layer sections, either on top of a lower-intermediate interconnect level or immediately before fabrication of an upper-intermediate interconnect level (224),
• fabricating an upper etch-barrier layer (211) on top of the upper-intermediate interconnect level (224), the upper etch-barrier layer being impermeable for the selective etchant,
• fabricating at least one respective etch opening in the upper and lower etch-barrier layers (211, 236), and at least one respective etch via connecting two respective etch openings (212, 214, 238, 240) on the upper and lower etch-barrier layers (211, 236),
• fabricating a lateral etch-barrier liner, which extends along side walls of the etch via and is impermeable for the selective etchant, and
• fabricating airgaps (248, 250, 252) on one or more interconnect levels (232), which are arranged below the lower etch-barrier layer (236), by applying the selective etchant through the etch via.