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US 2009/0243104 A1Published application
Forming thick metal interconnect structures for integrated circuits
AssigneeIntel Corporation
InventorKevin Lee
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Abstract
Embodiments of an apparatus and methods for forming thick metal interconnect structures for integrated structures are generally described herein. Other embodiments may be described and claimed.
Claims24
A method, comprising:
- depositing a first photodefinable dielectric layer adjacent to a first conductor;
- patterning and thermally curing the first photodefinable dielectric layer to expose a top surface of the first conductor;
- forming a seed layer over the first photodefinable dielectric layer and the top surface of the first conductor;
- depositing a mask layer on the seed layer;
- patterning the mask layer to expose the seed layer over the first conductor;
- forming a second conductor on the seed layer over the first conductor;
- removing the patterned mask layer;
- etching exposed portions of the seed layer;
- and
- depositing a second photodefinable dielectric layer directly adjacent to the second conductor.
7 more elements
A method of fabricating an interconnect structure comprising:
- depositing a photodefinable dielectric layer directly adjacent to a first conductor;
- patterning the photodefinable dielectric layer to expose a conductive region, forming a barrier seed stack over the photodefinable dielectric layer and the conductive region, depositing a photoresist layer on the barrier seed stack, patterning the photoresist layer to expose the barrier seed stack over the conductive region, forming a second conductor on the barrier seed stack over the conductive region, removing the patterned photoresist layer, etching exposed portions of the seed layer, and forming a second photodefinable dielectric layer directly adjacent to the second conductor.
An integrated circuit, comprising:
- a first conductor having a top surface and a side surface;
- a first photodefinable dielectric layer adjacent to the side surface of the first conductor;
- a seed layer over the top surface of the first conductor and over the first photodefinable dielectric layer;
- a second conductor on the seed layer;
- and
- a second photodefinable dielectric layer adjacent to the second conductor.
3 more elements
A device, comprising;
- a first self-passivating conductor having side surfaces;
- a first low thermal decomposition temperature dielectric layer adjacent to the side surfaces of the first self-passivating conductor;
- a second self-passivating conductor in contact with the first self-passivating conductor;
- and
- a second low thermal decomposition temperature dielectric layer adjacent to the second self-passivating conductor.
2 more elements
Dependencies are inferred from the claim text.