Clock Divider
AssigneeMicron Technology, Inc.
InventorFeng Lin
Life of this patent
Estimating the term…
Abstract
There is provided a true single phase logic clock divider that is configured to selectively divide a clock signal by increments of two, three, four, or six. Because the true single phase logic clock divider is based on true single phase logic instead of static logic, the true single phase logic clock divider is able to reliably divide clock signals that could not reliably be divided by clock dividers based on static logic gates. The true single phase logic clock divider is capable of reliably operating at frequencies of greater than or equal to two gigahertz.
Claims22
A clock divider comprising:
- a first circuit configured to receive an input clock signal and to selectively produce a first output clock signal having a frequency of approximately one half or approximately one fourth of a frequency of the input clock signal;
- and
- a second circuit configured to receive the input clock signal and to selectively produce a second output clock signal having a frequency of approximately one third or approximately one sixth of the frequency of the input clock signal.
A clock divider comprising:
- a first partial divider circuit configured to receive a single phase of a clock signal, a first data input, and a second data input;
- and
- a second partial divider circuit configured to receive the single phase of the clock signal, the first data input, and the second data input;
- wherein neither the first partial divider circuit or the second partial divider circuit receives any other clock signal or another phase of the clock signal.
A clock divider comprising two partial clock dividers each having four inputs configured to receive a respective input signal, the inputs consisting of:
- a reset configured to receive a reset signal;
- a clock input configured to receive a clock signal;
- a first data input configured to receive a first data signal;
- and
- a second data input configured to receive a second data signal.
A clock divider comprising:
- true single phase logic configured to selectively divide a clock signal by increments of two, three, four or six.
Dependencies are inferred from the claim text.