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US 2009/0222785 A1Published application
Method for shape and timing equivalent dimension extraction
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYing-Chou CHENG, Chih-Ming LAI, Ru-Gun LIU, Tsong-Hua OU, Min-Hong WU, Yih-Yuh DOONG, Hsiao-Shu CHAO, Yi-Kan CHENG, Yao-Ching KU, Cliff HOU
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Abstract
An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.
Claims20
An integrated circuit (IC) design method comprising:
- providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data;
- generating an effective rectangle layout to represent the IC layout contour;
- and
- simulating the IC device using the effective rectangular layout.
1 more element
An integrated circuit (IC) design method comprising:
- generating a channel contour of an IC device according to a design layout of the IC device and IC manufacturing data;
- extracting an effective channel rectangle from the channel contour;
- and
- simulating the channel contour of the IC device using the effective channel rectangle.
1 more element
An integrated circuit (IC) design method comprising:
- providing an IC channel design layout of an IC device;
- generating an IC channel contour based on the IC design layout and IC manufacturing data;
- generating an effective channel rectangle based on the IC channel contour;
- and
- generating an electrical parameter of the IC device based on the effective channel rectangle.
2 more elements
Dependencies are inferred from the claim text.